Merge pull request #386 from davine47/add-mill

Add mill to compile and test VexRiscv

.gitignore

@@ -48,6 +48,8 @@ obj_dir
 *.bin
 explor
 
+mill
+
 simWorkspace/
 tmp/
 /archive.tar.gz

README.md

@@ -441,6 +441,69 @@ To run it :
 sbt "test:runMain vexriscv.MuraxSim"
 ```
 
+## Build all above with mill
+
+Mill is a simple tool to build Scala/Java, also fits in off-line environment very well.
+
+Github url is here: https://github.com/com-lihaoyi/mill
+
+Document is here: https://mill-build.com/mill/Intro_to_Mill.html
+
+Download executable mill: 
+
+```sh
+curl --fail -L -o mill https://github.com/com-lihaoyi/mill/releases/download/0.11.6/0.11.6-assembly
+chmod +x mill
+```
+Using mill to generate the corresponding RTL as a `VexRiscv.v` file, run the following commands in the root directory of this repository:
+
+```sh
+./mill VexRiscv.runMain vexriscv.demo.GenFull
+```
+or
+
+```sh
+./mill VexRiscv.runMain vexriscv.demo.GenSmallest
+```
+
+Using mill to run tests (need java, scala, verilator), do :
+
+```sh
+export VEXRISCV_REGRESSION_SEED=42
+export VEXRISCV_REGRESSION_TEST_ID=
+./mill VexRiscv.test.testOnly vexriscv.TestIndividualFeatures
+```
+
+Using mill to generate the Briey SoC Hardware:
+
+```sh
+./mill VexRiscv.runMain vexriscv.demo.Briey
+```
+
+Using mill to generate the Murax SoC Hardware:
+
+```sh
+# To generate the SoC without any content in the ram
+./mill VexRiscv.runMain vexriscv.demo.Murax
+
+# To generate the SoC with a demo program already in ram
+./mill VexRiscv.runMain vexriscv.demo.MuraxWithRamInit
+
+# This will generate the Murax RTL + run its testbench. You need Verilator 3.9xx installated.
+./mill VexRiscv.test.runMain vexriscv.MuraxSim
+```
+
+Mill's IDE supports:
+
+```sh
+# Build Server Protocol (BSP)
+./mill mill.bsp.BSP/install
+
+# IntelliJ IDEA Support
+./mill mill.idea.GenIdea/idea
+```
+
+
 ## Running Linux
 
 A default configuration is located in `src/main/scala/vexriscv/demo/Linux.scala`.

build.sc

@@ -0,0 +1,28 @@
+import mill._, scalalib._
+
+val spinalVersion = "1.9.4"
+
+object ivys {
+  val sv = "2.11.12"
+  val spinalCore = ivy"com.github.spinalhdl::spinalhdl-core:$spinalVersion"
+  val spinalLib = ivy"com.github.spinalhdl::spinalhdl-lib:$spinalVersion"
+  val spinalPlugin = ivy"com.github.spinalhdl::spinalhdl-idsl-plugin:$spinalVersion"
+  val scalatest = ivy"org.scalatest::scalatest:3.2.5"
+  val macroParadise = ivy"org.scalamacros:::paradise:2.1.1"
+  val yaml = ivy"org.yaml:snakeyaml:1.8"
+}
+
+trait Common extends ScalaModule  {
+  override def scalaVersion = ivys.sv
+  override def scalacPluginIvyDeps = Agg(ivys.macroParadise, ivys.spinalPlugin)
+  override def ivyDeps = Agg(ivys.spinalCore, ivys.spinalLib, ivys.yaml, ivys.scalatest)
+  override def scalacOptions = Seq("-Xsource:2.11")
+}
+
+object VexRiscv extends Common with SbtModule{
+  override def millSourcePath = os.pwd
+  override def moduleDeps: Seq[JavaModule] = super.moduleDeps
+
+  object test extends SbtModuleTests with TestModule.ScalaTest
+}
+