From 3710fd34928f581470f43c000ea3d1fbec5e31ba Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Thu, 4 Feb 2021 12:41:31 +0100
Subject: [PATCH] fix synthesis bench

---
 src/main/scala/vexriscv/demo/SynthesisBench.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala
index d0a2118..e021e19 100644
--- a/src/main/scala/vexriscv/demo/SynthesisBench.scala
+++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala
@@ -217,7 +217,7 @@ object VexRiscvSynthesisBench {
             frequencyTarget = 50 MHz,
             vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
             workspacePath=workspace + "_area",
-            toplevelPath=rtl.getRtlPath(),
+            rtl=rtl,
             family=getFamilyName(),
             device="xcku035-fbva900-3-e"
           )
@@ -230,7 +230,7 @@ object VexRiscvSynthesisBench {
             frequencyTarget = 800 MHz,
             vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
             workspacePath=workspace + "_fmax",
-            toplevelPath=rtl.getRtlPath(),
+            rtl=rtl,
             family=getFamilyName(),
             device="xcku035-fbva900-3-e"
           )
@@ -243,7 +243,7 @@ object VexRiscvSynthesisBench {
             frequencyTarget = 50 MHz,
             vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
             workspacePath=workspace + "_area",
-            toplevelPath=rtl.getRtlPath(),
+            rtl=rtl,
             family=getFamilyName(),
             device="xcku3p-ffvd900-3-e"
           )
@@ -256,7 +256,7 @@ object VexRiscvSynthesisBench {
             frequencyTarget = 800 MHz,
             vivadoPath=sys.env.getOrElse("VIVADO_ARTIX_7_BIN", null),
             workspacePath=workspace + "_fmax",
-            toplevelPath=rtl.getRtlPath(),
+            rtl=rtl,
             family=getFamilyName(),
             device="xcku3p-ffvd900-3-e"
           )