diff --git a/build.sbt b/build.sbt
index f130951..d26c390 100644
--- a/build.sbt
+++ b/build.sbt
@@ -9,8 +9,8 @@ scalaVersion := "2.11.6"
 EclipseKeys.withSource := true
 
 libraryDependencies ++= Seq(
-  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.1",
-  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.1",
+  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.2",
+  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.2",
   "org.yaml" % "snakeyaml" % "1.8"
 )
 
diff --git a/src/test/scala/vexriscv/MuraxSim.scala b/src/test/scala/vexriscv/MuraxSim.scala
index a24ea2b..61bedaa 100644
--- a/src/test/scala/vexriscv/MuraxSim.scala
+++ b/src/test/scala/vexriscv/MuraxSim.scala
@@ -2,7 +2,7 @@ package vexriscv
 
 import spinal.sim._
 import spinal.core._
-import spinal.core.SimManagedApi._
+import spinal.core.sim._
 import vexriscv.demo.{Murax, MuraxConfig}
 
 import java.awt.Graphics
diff --git a/src/test/scala/vexriscv/TcpJtag.scala b/src/test/scala/vexriscv/TcpJtag.scala
index 1ce4806..89cec08 100644
--- a/src/test/scala/vexriscv/TcpJtag.scala
+++ b/src/test/scala/vexriscv/TcpJtag.scala
@@ -3,7 +3,7 @@ package vexriscv
 import java.io.{InputStream, OutputStream}
 import java.net.ServerSocket
 
-import spinal.core.SimManagedApi._
+import spinal.core.sim._
 import spinal.lib.com.jtag.Jtag
 
 import scala.concurrent.Future
diff --git a/src/test/scala/vexriscv/UartDecoder.scala b/src/test/scala/vexriscv/UartDecoder.scala
index fdb9b97..4b8558e 100644
--- a/src/test/scala/vexriscv/UartDecoder.scala
+++ b/src/test/scala/vexriscv/UartDecoder.scala
@@ -1,7 +1,7 @@
 package vexriscv
 
 import spinal.sim._
-import spinal.core.SimManagedApi._
+import spinal.core.sim._
 import spinal.core.{Bool, assert}
 
 object UartDecoder {
diff --git a/src/test/scala/vexriscv/UartEncoder.scala b/src/test/scala/vexriscv/UartEncoder.scala
index 8053b1e..c6cf1ce 100644
--- a/src/test/scala/vexriscv/UartEncoder.scala
+++ b/src/test/scala/vexriscv/UartEncoder.scala
@@ -1,8 +1,8 @@
 package vexriscv
 
 import spinal.sim._
+import spinal.core.sim._
 import spinal.core.Bool
-import spinal.core.SimManagedApi._
 
 object UartEncoder {
   def apply(uartPin : Bool, baudPeriod : Long) = fork{