diff --git a/src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala b/src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala
index 30a1bf3..0382018 100644
--- a/src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala
+++ b/src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala
@@ -42,6 +42,7 @@ object DBusSimpleBus{
     addressWidth = 32,
     dataWidth = 32).copy(
     useByteEnable = true,
+    useResponse = true,
     maximumPendingReadTransactions = 1
   )
 }
@@ -124,7 +125,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
 
     cmdStage.ready := mm.waitRequestn
     rsp.ready :=mm.readDataValid
-    rsp.error := False //TODO
+    rsp.error := mm.response =/= AvalonMM.Response.OKAY
     rsp.data := mm.readData
 
     mm
diff --git a/src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala b/src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala
index 4fea620..19c93cc 100644
--- a/src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala
+++ b/src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala
@@ -39,6 +39,7 @@ object IBusSimpleBus{
     addressWidth = 32,
     dataWidth = 32
   ).getReadOnlyConfig.copy(
+    useResponse = true,
     maximumPendingReadTransactions = 1
   )
 }
@@ -88,7 +89,7 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste
 
     rsp.ready := mm.readDataValid
     rsp.inst := mm.readData
-    rsp.error := False //TODO
+    rsp.error := mm.response =/= AvalonMM.Response.OKAY
 
     mm
   }
@@ -140,6 +141,8 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean)
       }
     }
 
+    fetch.insert(IBUS_ACCESS_ERROR) clearWhen(!fetch.arbitration.isValid) //Avoid interference with instruction injection from the debug plugin
+
     if(interfaceKeepData)
       fetch.arbitration.haltIt setWhen(fetch.arbitration.isValid && !iBus.rsp.ready)
     else
diff --git a/src/main/scala/VexRiscv/ip/DataCache.scala b/src/main/scala/VexRiscv/ip/DataCache.scala
index 1b69abf..af89f42 100644
--- a/src/main/scala/VexRiscv/ip/DataCache.scala
+++ b/src/main/scala/VexRiscv/ip/DataCache.scala
@@ -41,6 +41,7 @@ case class DataCacheConfig( cacheSize : Int,
     useByteEnable = true,
     constantBurstBehavior = true,
     burstOnBurstBoundariesOnly = true,
+    useResponse = true,
     maximumPendingReadTransactions = 2
   )
 }
@@ -275,7 +276,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
     cmd.ready := mm.waitRequestn
     rsp.valid := mm.readDataValid
     rsp.data  := mm.readData
-    rsp.error := False
+    rsp.error := mm.response =/= AvalonMM.Response.OKAY
 
     mm
   }
diff --git a/src/main/scala/VexRiscv/ip/InstructionCache.scala b/src/main/scala/VexRiscv/ip/InstructionCache.scala
index 63a5f5c..813df19 100644
--- a/src/main/scala/VexRiscv/ip/InstructionCache.scala
+++ b/src/main/scala/VexRiscv/ip/InstructionCache.scala
@@ -37,6 +37,7 @@ case class InstructionCacheConfig( cacheSize : Int,
     dataWidth = memDataWidth,
     burstCountWidth = log2Up(burstSize + 1)).getReadOnlyConfig.copy(
     linewrapBursts = wrappedMemAccess,
+    useResponse = true,
     constantBurstBehavior = true
   )
 
@@ -154,7 +155,7 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
     cmd.ready := mm.waitRequestn
     rsp.valid := mm.readDataValid
     rsp.data := mm.readData
-    rsp.error := False
+    rsp.error := mm.response =/= AvalonMM.Response.OKAY
     mm
   }
 }
diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp
index 8d04aa1..e37abf2 100644
--- a/src/test/cpp/regression/main.cpp
+++ b/src/test/cpp/regression/main.cpp
@@ -528,9 +528,11 @@ public:
 			IBusSimpleAvalonRsp rsp = rsps.front(); rsps.pop();
 			top->iBusAvalon_readDataValid = 1;
 			top->iBusAvalon_readData = rsp.data;
+			top->iBusAvalon_response = rsp.error ? 3 : 0;
 		} else {
 			top->iBusAvalon_readDataValid = 0;
 			top->iBusAvalon_readData = VL_RANDOM_I(32);
+			top->iBusAvalon_response = VL_RANDOM_I(2);
 		}
 		if(ws->iStall)
 			top->iBusAvalon_waitRequestn = VL_RANDOM_I(7) < 100;
@@ -625,8 +627,9 @@ public:
 		if(!tasks.empty() && (!ws->iStall || VL_RANDOM_I(7) < 100)){
 			uint32_t &address = tasks.front().address;
 			uint32_t &pendingCount = tasks.front().pendingCount;
+			bool error;
 			ws->iBusAccess(address,&top->iBusAvalon_readData,&error);
-			//top->iBus_rsp_payload_error = error; //TODO
+			top->iBusAvalon_response = error ? 3 : 0;
 			pendingCount--;
 			address = (address & ~0x1F) + ((address + 4) & 0x1F);
 			top->iBusAvalon_readDataValid = 1;
@@ -723,9 +726,11 @@ public:
 			DBusSimpleAvalonRsp rsp = rsps.front(); rsps.pop();
 			top->dBusAvalon_readDataValid = 1;
 			top->dBusAvalon_readData = rsp.data;
+			top->dBusAvalon_response = rsp.error ? 3 : 0;
 		} else {
 			top->dBusAvalon_readDataValid = 0;
 			top->dBusAvalon_readData = VL_RANDOM_I(32);
+			top->dBusAvalon_response = VL_RANDOM_I(2);
 		}
 		if(ws->iStall)
 			top->dBusAvalon_waitRequestn = VL_RANDOM_I(7) < 100;
@@ -837,13 +842,13 @@ public:
 		if(!rsps.empty() && (!ws->dStall || VL_RANDOM_I(7) < 100)){
 			DBusCachedAvalonTask rsp = rsps.front();
 			rsps.pop();
-			//top->dBus_rsp_payload_error = rsp.error; //TODO
+			top->dBusAvalon_response = rsp.error ? 3 : 0;
 			top->dBusAvalon_readData = rsp.data;
 			top->dBusAvalon_readDataValid = 1;
 		} else{
 			top->dBusAvalon_readDataValid = 0;
 			top->dBusAvalon_readData = VL_RANDOM_I(32);
-			//top->dBus_rsp_payload_error = VL_RANDOM_I(1); //TODO
+			top->dBusAvalon_response = VL_RANDOM_I(2); //TODO
 		}
 
 		top->dBusAvalon_waitRequestn = (ws->dStall ? VL_RANDOM_I(7) < 100 : 1);