diff --git a/src/main/scala/VexRiscv/demo/GenFull.scala b/src/main/scala/VexRiscv/demo/GenFull.scala index 6477ef7..df06357 100644 --- a/src/main/scala/VexRiscv/demo/GenFull.scala +++ b/src/main/scala/VexRiscv/demo/GenFull.scala @@ -9,87 +9,87 @@ import spinal.core._ * Created by spinalvm on 15.06.17. */ object GenFull extends App{ - SpinalVerilog( - gen = new VexRiscv( - config = VexRiscvConfig( - plugins = List( - new PcManagerSimplePlugin(0x00000000l, false), - new IBusCachedPlugin( - config = InstructionCacheConfig( - cacheSize = 4096, - bytePerLine =32, - wayCount = 1, - wrappedMemAccess = true, - addressWidth = 32, - cpuDataWidth = 32, - memDataWidth = 32, - catchIllegalAccess = true, - catchAccessFault = true, - catchMemoryTranslationMiss = true, - asyncTagMemory = false, - twoStageLogic = true - ), - askMemoryTranslation = true, - memoryTranslatorPortConfig = MemoryTranslatorPortConfig( - portTlbSize = 4 - ) + def cpu() = new VexRiscv( + config = VexRiscvConfig( + plugins = List( + new PcManagerSimplePlugin(0x00000000l, false), + new IBusCachedPlugin( + config = InstructionCacheConfig( + cacheSize = 4096, + bytePerLine =32, + wayCount = 1, + wrappedMemAccess = true, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchIllegalAccess = true, + catchAccessFault = true, + catchMemoryTranslationMiss = true, + asyncTagMemory = false, + twoStageLogic = true ), - new DBusCachedPlugin( - config = new DataCacheConfig( - cacheSize = 4096, - bytePerLine = 32, - wayCount = 1, - addressWidth = 32, - cpuDataWidth = 32, - memDataWidth = 32, - catchAccessError = true, - catchIllegal = true, - catchUnaligned = true, - catchMemoryTranslationMiss = true - ), - memoryTranslatorPortConfig = MemoryTranslatorPortConfig( - portTlbSize = 6 - ) + askMemoryTranslation = true, + memoryTranslatorPortConfig = MemoryTranslatorPortConfig( + portTlbSize = 4 + ) + ), + new DBusCachedPlugin( + config = new DataCacheConfig( + cacheSize = 4096, + bytePerLine = 32, + wayCount = 1, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchAccessError = true, + catchIllegal = true, + catchUnaligned = true, + catchMemoryTranslationMiss = true ), - new MemoryTranslatorPlugin( - tlbSize = 32, - virtualRange = _(31 downto 28) === 0xC, - ioRange = _(31 downto 28) === 0xF - ), - new DecoderSimplePlugin( - catchIllegalInstruction = true - ), - new RegFilePlugin( - regFileReadyKind = Plugin.SYNC, - zeroBoot = true - ), - new IntAluPlugin, - new SrcPlugin( - separatedAddSub = false, - executeInsertion = true - ), - new FullBarrielShifterPlugin, - new HazardSimplePlugin( - bypassExecute = true, - bypassMemory = true, - bypassWriteBack = true, - bypassWriteBackBuffer = true, - pessimisticUseSrc = false, - pessimisticWriteRegFile = false, - pessimisticAddressMatch = false - ), - new MulPlugin, - new DivPlugin, - new CsrPlugin(CsrPluginConfig.all), - new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), - new BranchPlugin( - earlyBranch = false, - catchAddressMisaligned = true, - prediction = DYNAMIC - ), - new YamlPlugin("cpu0.yaml") - ) + memoryTranslatorPortConfig = MemoryTranslatorPortConfig( + portTlbSize = 6 + ) + ), + new MemoryTranslatorPlugin( + tlbSize = 32, + virtualRange = _(31 downto 28) === 0xC, + ioRange = _(31 downto 28) === 0xF + ), + new DecoderSimplePlugin( + catchIllegalInstruction = true + ), + new RegFilePlugin( + regFileReadyKind = Plugin.SYNC, + zeroBoot = true + ), + new IntAluPlugin, + new SrcPlugin( + separatedAddSub = false, + executeInsertion = true + ), + new FullBarrielShifterPlugin, + new HazardSimplePlugin( + bypassExecute = true, + bypassMemory = true, + bypassWriteBack = true, + bypassWriteBackBuffer = true, + pessimisticUseSrc = false, + pessimisticWriteRegFile = false, + pessimisticAddressMatch = false + ), + new MulPlugin, + new DivPlugin, + new CsrPlugin(CsrPluginConfig.all), + new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), + new BranchPlugin( + earlyBranch = false, + catchAddressMisaligned = true, + prediction = DYNAMIC + ), + new YamlPlugin("cpu0.yaml") ) ) ) + + SpinalVerilog(cpu()) } diff --git a/src/main/scala/VexRiscv/demo/GenFullNoMmu.scala b/src/main/scala/VexRiscv/demo/GenFullNoMmu.scala new file mode 100644 index 0000000..73ece55 --- /dev/null +++ b/src/main/scala/VexRiscv/demo/GenFullNoMmu.scala @@ -0,0 +1,86 @@ +package VexRiscv.demo + +import VexRiscv.Plugin._ +import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig} +import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig} +import spinal.core._ + +/** + * Created by spinalvm on 15.06.17. + */ +object GenFullNoMmu extends App{ + def cpu() = new VexRiscv( + config = VexRiscvConfig( + plugins = List( + new PcManagerSimplePlugin(0x00000000l, false), + new IBusCachedPlugin( + config = InstructionCacheConfig( + cacheSize = 4096, + bytePerLine =32, + wayCount = 1, + wrappedMemAccess = true, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchIllegalAccess = true, + catchAccessFault = true, + catchMemoryTranslationMiss = true, + asyncTagMemory = false, + twoStageLogic = true + ) + ), + new DBusCachedPlugin( + config = new DataCacheConfig( + cacheSize = 4096, + bytePerLine = 32, + wayCount = 1, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchAccessError = true, + catchIllegal = true, + catchUnaligned = true, + catchMemoryTranslationMiss = true + ) + ), + new StaticMemoryTranslatorPlugin( + ioRange = _(31 downto 28) === 0xF + ), + new DecoderSimplePlugin( + catchIllegalInstruction = true + ), + new RegFilePlugin( + regFileReadyKind = Plugin.SYNC, + zeroBoot = true + ), + new IntAluPlugin, + new SrcPlugin( + separatedAddSub = false, + executeInsertion = true + ), + new FullBarrielShifterPlugin, + new HazardSimplePlugin( + bypassExecute = true, + bypassMemory = true, + bypassWriteBack = true, + bypassWriteBackBuffer = true, + pessimisticUseSrc = false, + pessimisticWriteRegFile = false, + pessimisticAddressMatch = false + ), + new MulPlugin, + new DivPlugin, + new CsrPlugin(CsrPluginConfig.all), + new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), + new BranchPlugin( + earlyBranch = false, + catchAddressMisaligned = true, + prediction = DYNAMIC + ), + new YamlPlugin("cpu0.yaml") + ) + ) + ) + + SpinalVerilog(cpu()) +} diff --git a/src/main/scala/VexRiscv/demo/GenSmallest.scala b/src/main/scala/VexRiscv/demo/GenSmallest.scala index 86b6ae0..cba57d1 100644 --- a/src/main/scala/VexRiscv/demo/GenSmallest.scala +++ b/src/main/scala/VexRiscv/demo/GenSmallest.scala @@ -8,49 +8,49 @@ import spinal.core._ * Created by spinalvm on 15.06.17. */ object GenSmallest extends App{ - SpinalVerilog( - gen = new VexRiscv( - config = VexRiscvConfig( - plugins = List( - new PcManagerSimplePlugin(0x00000000l, true), - new IBusSimplePlugin( - interfaceKeepData = false, - catchAccessFault = false - ), - new DBusSimplePlugin( - catchAddressMisaligned = false, - catchAccessFault = false - ), - new CsrPlugin(CsrPluginConfig.smallest), - new DecoderSimplePlugin( - catchIllegalInstruction = false - ), - new RegFilePlugin( - regFileReadyKind = Plugin.SYNC, - zeroBoot = true - ), - new IntAluPlugin, - new SrcPlugin( - separatedAddSub = false - ), - new LightShifterPlugin, - new HazardSimplePlugin( - bypassExecute = false, - bypassMemory = false, - bypassWriteBack = false, - bypassWriteBackBuffer = false, - pessimisticUseSrc = false, - pessimisticWriteRegFile = false, - pessimisticAddressMatch = false - ), - new BranchPlugin( - earlyBranch = false, - catchAddressMisaligned = false, - prediction = NONE - ), - new YamlPlugin("cpu0.yaml") - ) + def cpu() = new VexRiscv( + config = VexRiscvConfig( + plugins = List( + new PcManagerSimplePlugin(0x00000000l, true), + new IBusSimplePlugin( + interfaceKeepData = false, + catchAccessFault = false + ), + new DBusSimplePlugin( + catchAddressMisaligned = false, + catchAccessFault = false + ), + new CsrPlugin(CsrPluginConfig.smallest), + new DecoderSimplePlugin( + catchIllegalInstruction = false + ), + new RegFilePlugin( + regFileReadyKind = Plugin.SYNC, + zeroBoot = true + ), + new IntAluPlugin, + new SrcPlugin( + separatedAddSub = false + ), + new LightShifterPlugin, + new HazardSimplePlugin( + bypassExecute = false, + bypassMemory = false, + bypassWriteBack = false, + bypassWriteBackBuffer = false, + pessimisticUseSrc = false, + pessimisticWriteRegFile = false, + pessimisticAddressMatch = false + ), + new BranchPlugin( + earlyBranch = false, + catchAddressMisaligned = false, + prediction = NONE + ), + new YamlPlugin("cpu0.yaml") ) ) ) + + SpinalVerilog(cpu()) } diff --git a/src/main/scala/VexRiscv/demo/GenSmallestNoCsr.scala b/src/main/scala/VexRiscv/demo/GenSmallestNoCsr.scala new file mode 100644 index 0000000..1039016 --- /dev/null +++ b/src/main/scala/VexRiscv/demo/GenSmallestNoCsr.scala @@ -0,0 +1,55 @@ +package VexRiscv.demo + +import VexRiscv.Plugin._ +import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig} +import spinal.core._ + +/** + * Created by spinalvm on 15.06.17. + */ +object GenSmallestNoCsr extends App{ + def cpu() = new VexRiscv( + config = VexRiscvConfig( + plugins = List( + new PcManagerSimplePlugin(0x00000000l, true), + new IBusSimplePlugin( + interfaceKeepData = false, + catchAccessFault = false + ), + new DBusSimplePlugin( + catchAddressMisaligned = false, + catchAccessFault = false + ), + new DecoderSimplePlugin( + catchIllegalInstruction = false + ), + new RegFilePlugin( + regFileReadyKind = Plugin.SYNC, + zeroBoot = true + ), + new IntAluPlugin, + new SrcPlugin( + separatedAddSub = false + ), + new LightShifterPlugin, + new HazardSimplePlugin( + bypassExecute = false, + bypassMemory = false, + bypassWriteBack = false, + bypassWriteBackBuffer = false, + pessimisticUseSrc = false, + pessimisticWriteRegFile = false, + pessimisticAddressMatch = false + ), + new BranchPlugin( + earlyBranch = false, + catchAddressMisaligned = false, + prediction = NONE + ), + new YamlPlugin("cpu0.yaml") + ) + ) + ) + + SpinalVerilog(cpu()) +} diff --git a/src/main/scala/VexRiscv/demo/SynthesisBench.scala b/src/main/scala/VexRiscv/demo/SynthesisBench.scala new file mode 100644 index 0000000..d6cbb34 --- /dev/null +++ b/src/main/scala/VexRiscv/demo/SynthesisBench.scala @@ -0,0 +1,45 @@ +package VexRiscv.demo + +import spinal.core.SpinalVerilog +import spinal.lib.eda.bench.{Bench, AlteraStdTargets, Rtl} + +/** + * Created by PIC32F_USER on 16/07/2017. + */ +object SynthesisBench { + def main(args: Array[String]) { + val smallestNoCsr = new Rtl { + override def getName(): String = "VexRiscv smallest no CSR" + override def getRtlPath(): String = "VexRiscvSmallestNoCsr.v" + SpinalVerilog(GenSmallestNoCsr.cpu().setDefinitionName(getRtlPath().split("\\.").head)) + } + + val smallest = new Rtl { + override def getName(): String = "VexRiscv smallest" + override def getRtlPath(): String = "VexRiscvSmallest.v" + SpinalVerilog(GenSmallest.cpu().setDefinitionName(getRtlPath().split("\\.").head)) + } + + val fullNoMmu = new Rtl { + override def getName(): String = "VexRiscv full no MMU" + override def getRtlPath(): String = "VexRiscvFullNoMmu.v" + SpinalVerilog(GenFullNoMmu.cpu().setDefinitionName(getRtlPath().split("\\.").head)) + } + + val full = new Rtl { + override def getName(): String = "VexRiscv full" + override def getRtlPath(): String = "VexRiscvFull.v" + SpinalVerilog(GenFull.cpu().setDefinitionName(getRtlPath().split("\\.").head)) + } + + val rtls = List(smallestNoCsr, smallest, fullNoMmu, full) + + val targets = AlteraStdTargets( + quartusCycloneIIPath = "D:/altera/13.0sp1/quartus/bin64", + quartusCycloneIVPath = "D:/altera_lite/15.1/quartus/bin64", + quartusCycloneVPath = "D:/altera_lite/15.1/quartus/bin64" + ) + + Bench(rtls, targets, "E:/tmp/") + } +}