diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
index a12b696..85407de 100644
--- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
@@ -46,7 +46,7 @@ case class CsrPluginConfig(
                             misaExtensionsInit  : Int,
                             misaAccess          : CsrAccess,
                             mtvecAccess         : CsrAccess,
-                            mtvecInit           : BigInt,
+                            var mtvecInit       : BigInt,
                             mepcAccess          : CsrAccess,
                             mscratchGen         : Boolean,
                             mcauseAccess        : CsrAccess,
@@ -458,7 +458,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
   }
 
 
-  override def getVexRiscvRegressionArgs() = List(s"SUPERVISOR=${if(config.supervisorGen) "yes" else "no"}, CSR=yes")
+  override def getVexRiscvRegressionArgs() = List(s"SUPERVISOR=${if(config.supervisorGen) "yes" else "no"} CSR=yes")
 
   var exceptionPendings : Vec[Bool] = null
   override def isExceptionPending(stage : Stage): Bool = exceptionPendings(pipeline.stages.indexOf(stage))
diff --git a/src/main/scala/vexriscv/plugin/MmuPlugin.scala b/src/main/scala/vexriscv/plugin/MmuPlugin.scala
index aea906f..8057d17 100644
--- a/src/main/scala/vexriscv/plugin/MmuPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/MmuPlugin.scala
@@ -38,7 +38,7 @@ case class MmuPort(bus : MemoryTranslatorBus, priority : Int, args : MmuPortConf
 
 case class MmuPortConfig(portTlbSize : Int, latency : Int = 0, earlyRequireMmuLockup : Boolean = false, earlyCacheHits : Boolean = false)
 
-class MmuPlugin(ioRange : UInt => Bool,
+class MmuPlugin(var ioRange : UInt => Bool,
                 virtualRange : UInt => Bool = address => True,
 //                allowUserIo : Boolean = false,
                 enableMmuInMachineMode : Boolean = false) extends Plugin[VexRiscv] with MemoryTranslator {