From 3ae51cdeb84e3d3686f3ff4d2b3739276166cdd6 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Wed, 8 Feb 2023 14:44:04 +0100
Subject: [PATCH] Fix fpu csr access on fs===0 now also trap

---
 src/main/scala/vexriscv/plugin/FpuPlugin.scala | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/vexriscv/plugin/FpuPlugin.scala b/src/main/scala/vexriscv/plugin/FpuPlugin.scala
index 8ea478e..6989753 100644
--- a/src/main/scala/vexriscv/plugin/FpuPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/FpuPlugin.scala
@@ -229,13 +229,15 @@ class FpuPlugin(externalFpu : Boolean = false,
       service.r(CSR.SSTATUS, 31, sd)
       service.r(CSR.MSTATUS, 31, sd)
 
-      when(fs === 0) {
-        for (csr <- List(CSR.FRM, CSR.FCSR, CSR.FFLAGS)) {
-          service.during(csr) {
-            service.forceFailCsr()
-          }
+      val accessFpuCsr = False
+      for (csr <- List(CSR.FRM, CSR.FCSR, CSR.FFLAGS)) {
+        service.during(csr) {
+          accessFpuCsr := True
         }
       }
+      when(accessFpuCsr && fs === 0) {
+        service.forceFailCsr()
+      }
     }
 
     decode plug new Area{