From 3b3bbd48b97a5f3a91ba7fe47e737a1076f5421f Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 20 Jan 2018 18:29:33 +0100 Subject: [PATCH] SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files --- .gitignore | 2 +- build.sbt | 4 ++-- scripts/Murax/iCE40-hx8k_breakout_board/makefile | 7 +++++-- scripts/Murax/iCE40HX8K-EVB/makefile | 3 +++ src/main/scala/vexriscv/TestsWorkspace.scala | 4 ++-- src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala | 2 +- src/main/scala/vexriscv/demo/GenFull.scala | 2 +- src/main/scala/vexriscv/demo/GenFullNoMmu.scala | 2 +- src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala | 2 +- src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala | 2 +- src/main/scala/vexriscv/demo/GenSmallest.scala | 2 +- src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala | 2 +- src/main/scala/vexriscv/demo/Murax.scala | 4 ++-- src/test/cpp/briey/makefile | 5 ++++- src/test/cpp/murax/makefile | 7 +++++-- src/test/cpp/regression/makefile | 5 ++++- src/test/scala/vexriscv/MuraxSim.scala | 4 ++-- 17 files changed, 37 insertions(+), 22 deletions(-) diff --git a/.gitignore b/.gitignore index 86e1cdd..60ad8ba 100644 --- a/.gitignore +++ b/.gitignore @@ -41,7 +41,7 @@ obj_dir *.regTrace *.tcl *.o - +*.bin simWorkspace/ tmp/ diff --git a/build.sbt b/build.sbt index 85a7fcc..2ad109c 100644 --- a/build.sbt +++ b/build.sbt @@ -9,8 +9,8 @@ scalaVersion := "2.11.6" EclipseKeys.withSource := true libraryDependencies ++= Seq( - "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.1.2", - "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.1.2", + "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.1.3", + "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.1.3", "org.yaml" % "snakeyaml" % "1.8" ) diff --git a/scripts/Murax/iCE40-hx8k_breakout_board/makefile b/scripts/Murax/iCE40-hx8k_breakout_board/makefile index 3f7c71b..39bd3e9 100644 --- a/scripts/Murax/iCE40-hx8k_breakout_board/makefile +++ b/scripts/Murax/iCE40-hx8k_breakout_board/makefile @@ -8,8 +8,10 @@ generate : ../../../Murax.v : (cd ../../..; sbt "run-main vexriscv.demo.Murax") -bin/toplevel.blif : ${VERILOG} +bin/toplevel.blif : ${VERILOG} ../../../Murax.v*.bin mkdir -p bin + rm -f Murax.v*.bin + cp ../../../Murax.v*.bin . | true yosys -v3 -p "synth_ice40 -top toplevel -blif bin/toplevel.blif" ${VERILOG} bin/toplevel.asc : toplevel.pcf bin/toplevel.blif @@ -27,4 +29,5 @@ prog : bin/toplevel.bin sudo iceprog -S bin/toplevel.bin clean : - rm -rf bin \ No newline at end of file + rm -rf bin + rm -f Murax.v*.bin \ No newline at end of file diff --git a/scripts/Murax/iCE40HX8K-EVB/makefile b/scripts/Murax/iCE40HX8K-EVB/makefile index e8becb7..255c506 100644 --- a/scripts/Murax/iCE40HX8K-EVB/makefile +++ b/scripts/Murax/iCE40HX8K-EVB/makefile @@ -10,6 +10,8 @@ generate : bin/toplevel.blif : ${VERILOG} mkdir -p bin + rm -f Murax.v*.bin + cp ../../../Murax.v*.bin . | true yosys -v3 -p "synth_ice40 -top toplevel -blif bin/toplevel.blif" ${VERILOG} bin/toplevel.asc : toplevel.pcf bin/toplevel.blif @@ -31,3 +33,4 @@ sudo-prog : bin/toplevel.bin clean : rm -rf bin + rm -f Murax.v*.bin diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index b6fcfb7..6f5e287 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -96,7 +96,7 @@ object TestsWorkspace { ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( @@ -197,7 +197,7 @@ object TestsWorkspace { ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala b/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala index da5b293..ba19991 100644 --- a/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala +++ b/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala @@ -29,7 +29,7 @@ object GenCustomSimdAdd extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenFull.scala b/src/main/scala/vexriscv/demo/GenFull.scala index 1d83903..ede0f80 100644 --- a/src/main/scala/vexriscv/demo/GenFull.scala +++ b/src/main/scala/vexriscv/demo/GenFull.scala @@ -63,7 +63,7 @@ object GenFull extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenFullNoMmu.scala b/src/main/scala/vexriscv/demo/GenFullNoMmu.scala index aee85d6..c40c1b9 100644 --- a/src/main/scala/vexriscv/demo/GenFullNoMmu.scala +++ b/src/main/scala/vexriscv/demo/GenFullNoMmu.scala @@ -54,7 +54,7 @@ object GenFullNoMmu extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala b/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala index d3a5945..923540b 100644 --- a/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala +++ b/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala @@ -29,7 +29,7 @@ object GenFullNoMmuNoCache extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala b/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala index d5aeb08..8a45aa3 100644 --- a/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala +++ b/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala @@ -29,7 +29,7 @@ object GenSmallAndProductive extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenSmallest.scala b/src/main/scala/vexriscv/demo/GenSmallest.scala index 92e6bb7..6e86db9 100644 --- a/src/main/scala/vexriscv/demo/GenSmallest.scala +++ b/src/main/scala/vexriscv/demo/GenSmallest.scala @@ -29,7 +29,7 @@ object GenSmallest extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala b/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala index 096394a..470ac3d 100644 --- a/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala +++ b/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala @@ -28,7 +28,7 @@ object GenSmallestNoCsr extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 9022f36..aa0bd66 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -71,7 +71,7 @@ object MuraxConfig{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( @@ -325,4 +325,4 @@ object MuraxWithRamInit{ def main(args: Array[String]) { SpinalVerilog(Murax(MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex"))) } -} \ No newline at end of file +} diff --git a/src/test/cpp/briey/makefile b/src/test/cpp/briey/makefile index 29d7d76..12d4c97 100644 --- a/src/test/cpp/briey/makefile +++ b/src/test/cpp/briey/makefile @@ -45,12 +45,15 @@ all: clean compile run: compile ./obj_dir/VBriey -verilate: +verilate: ../../../../Briey.v + rm -f Briey.v*.bin + cp ../../../../Briey.v*.bin . | true verilator -cc ../../../../Briey.v -CFLAGS -std=c++11 ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp compile: verilate make -j -C obj_dir/ -f VBriey.mk VBriey clean: + rm -f Briey.v*.bin rm -rf obj_dir diff --git a/src/test/cpp/murax/makefile b/src/test/cpp/murax/makefile index 83b5639..71a5cd6 100644 --- a/src/test/cpp/murax/makefile +++ b/src/test/cpp/murax/makefile @@ -28,12 +28,15 @@ all: clean compile run: compile ./obj_dir/VMurax -verilate: - verilator -cc ../../../../Murax.v -CFLAGS -std=c++11 ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp +verilate: ../../../../Murax.v + rm -f Murax.v*.bin + cp ../../../../Murax.v*.bin . | true + verilator -I../../../.. -cc ../../../../Murax.v -CFLAGS -std=c++11 ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp compile: verilate make -j -C obj_dir/ -f VMurax.mk VMurax clean: rm -rf obj_dir + rm -f Murax.v*.bin diff --git a/src/test/cpp/regression/makefile b/src/test/cpp/regression/makefile index c56b846..04555fc 100644 --- a/src/test/cpp/regression/makefile +++ b/src/test/cpp/regression/makefile @@ -99,7 +99,9 @@ all: clean run run: compile ./obj_dir/VVexRiscv -verilate: +verilate: ../../../../VexRiscv.v + rm -f VexRiscv.v*.bin + cp ../../../../VexRiscv.v*.bin . | true verilator -cc ../../../../VexRiscv.v -O3 -CFLAGS -std=c++11 -LDFLAGS -pthread ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-UNOPTFLAT -Wno-WIDTH --x-assign unique --exe main.cpp compile: verilate @@ -107,4 +109,5 @@ compile: verilate clean: rm -rf obj_dir + rm -f VexRiscv.v*.bin diff --git a/src/test/scala/vexriscv/MuraxSim.scala b/src/test/scala/vexriscv/MuraxSim.scala index 375f8dd..467cfdb 100644 --- a/src/test/scala/vexriscv/MuraxSim.scala +++ b/src/test/scala/vexriscv/MuraxSim.scala @@ -20,8 +20,8 @@ import scala.collection.mutable object MuraxSim { def main(args: Array[String]): Unit = { - def config = MuraxConfig.default.copy(onChipRamSize = 256 kB) -// def config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex") +// def config = MuraxConfig.default.copy(onChipRamSize = 256 kB) + def config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex") SimConfig.allOptimisation.compile(new Murax(config)).doSimUntilVoid{dut => val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong