From 95c3e436dceea548702a882f0a3c44d05af482a5 Mon Sep 17 00:00:00 2001
From: Tom Verbeure <hombre+github@gmail.com>
Date: Sat, 23 Mar 2019 22:32:48 +0000
Subject: [PATCH 1/3] Make toPipelinedMemoryBus() just like the other busses

---
 src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
index 636b193..5d6ad0b 100644
--- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
@@ -59,6 +59,11 @@ object IBusSimpleBus{
     useBTE = true,
     useCTI = true
   )
+
+  def getPipelinedMemoryBusConfig() = PipelinedMemoryBusConfig(
+    addressWidth = 32,
+    dataWidth = 32
+  )
 }
 
 
@@ -136,7 +141,8 @@ case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle wit
   }
 
   def toPipelinedMemoryBus(): PipelinedMemoryBus = {
-    val bus = PipelinedMemoryBus(32,32)
+    val pipelinedMemoryBusConfig = IBusSimpleBus.getPipelinedMemoryBusConfig()
+    val bus = PipelinedMemoryBus(pipelinedMemoryBusConfig)
     bus.cmd.arbitrationFrom(cmd)
     bus.cmd.address := cmd.pc.resized
     bus.cmd.write := False
@@ -281,4 +287,4 @@ class IBusSimplePlugin(resetVector : BigInt,
       }
     }
   }
-}
\ No newline at end of file
+}

From 1afad4f240fbe8899f46f1d5fc867370ae32974f Mon Sep 17 00:00:00 2001
From: Tom Verbeure <hombre+github@gmail.com>
Date: Sat, 23 Mar 2019 22:34:22 +0000
Subject: [PATCH 2/3] Ignore vim backup files.

---
 .gitignore | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.gitignore b/.gitignore
index eaab2e7..2737be0 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,6 +1,7 @@
 *.class
 *.log
 *.bak
+.*.swp
 
 # sbt specific
 .cache/
@@ -46,4 +47,4 @@ obj_dir
 simWorkspace/
 tmp/
 /archive.tar.gz
-*.out32
\ No newline at end of file
+*.out32

From ea62fd0e16764b3921404081f6b8afbdbc308172 Mon Sep 17 00:00:00 2001
From: Tom Verbeure <hombre+github@gmail.com>
Date: Sat, 23 Mar 2019 23:36:13 +0000
Subject: [PATCH 3/3] Same thing for DBusSimpleBus.

---
 src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
index eb4ce46..44b9ee1 100644
--- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
@@ -63,6 +63,12 @@ object DBusSimpleBus{
     useBTE = true,
     useCTI = true
   )
+
+  def getPipelinedMemoryBusConfig() = PipelinedMemoryBusConfig(
+    addressWidth = 32,
+    dataWidth = 32
+  )
+
 }
 
 case class DBusSimpleBus() extends Bundle with IMasterSlave{
@@ -178,7 +184,8 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
   }
 
   def toPipelinedMemoryBus() : PipelinedMemoryBus = {
-    val bus = PipelinedMemoryBus(32,32)
+    val pipelinedMemoryBusConfig = DBusSimpleBus.getPipelinedMemoryBusConfig()
+    val bus = PipelinedMemoryBus(pipelinedMemoryBusConfig)
     bus.cmd.valid := cmd.valid
     bus.cmd.write := cmd.wr
     bus.cmd.address := cmd.address.resized