From 3d710451593aef7ba0eccc6bf782622f363698d9 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 1 Dec 2018 18:24:33 +0100 Subject: [PATCH] DebugPlugin doesn't require memory/writeback stage anymore --- src/main/scala/vexriscv/plugin/DebugPlugin.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala index 7d28b24..56f2795 100644 --- a/src/main/scala/vexriscv/plugin/DebugPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala @@ -141,7 +141,7 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount : val haltIt = RegInit(False) val stepIt = RegInit(False) - val isPipActive = RegNext(List(decode,execute, memory, writeBack).map(_.arbitration.isValid).orR) + val isPipActive = RegNext(stages.map(_.arbitration.isValid).orR) val isPipBusy = isPipActive || RegNext(isPipActive) val haltedByBreak = RegInit(False) @@ -152,8 +152,8 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount : hardwareBreakpoints.foreach(_.valid init(False)) val busReadDataReg = Reg(Bits(32 bit)) - when(writeBack.arbitration.isValid) { - busReadDataReg := writeBack.output(REGFILE_WRITE_DATA) + when(stages.last.arbitration.isValid) { + busReadDataReg := stages.last.output(REGFILE_WRITE_DATA) } io.bus.cmd.ready := True io.bus.rsp.data := busReadDataReg @@ -199,7 +199,7 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount : when(execute.arbitration.isValid && execute.input(DO_EBREAK)){ execute.arbitration.haltByOther := True busReadDataReg := execute.input(PC).asBits - when(List(memory, writeBack).map(_.arbitration.isValid).orR === False){ + when(stagesFromExecute.tail.map(_.arbitration.isValid).orR === False){ iBusFetcher.flushIt() iBusFetcher.haltIt() execute.arbitration.flushAll := True