From 3d97c1f2f2333078cddcd8127a11e6c432299e1b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 2 Feb 2018 14:47:07 +0100 Subject: [PATCH] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index ddbf33b..325b931 100644 --- a/README.md +++ b/README.md @@ -99,7 +99,7 @@ There is a summary of the configuration which produce 1.40 DMIPS : - memory load values are bypassed in the WB stage (late result) - 33 cycle division with bypassing in the M stage (late result) - single cycle multiplication with bypassing in the WB stage (late result) -- dynamic branch prediction done in the D stage with an direct mapped 2 bit branch history cache +- dynamic branch prediction done in the F stage with an direct mapped target buffer cache (no penalities on corrects predictions) ## Dependencies