From 1175f195dfcd24a63fd9f9ee84b6e7145e2719b0 Mon Sep 17 00:00:00 2001
From: MrJake222 <norbertzpilicy@gmail.com>
Date: Tue, 4 Jun 2024 23:11:10 +0200
Subject: [PATCH] Exposed write mask on default iBus

---
 src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
index 5733ac7..0e7d123 100644
--- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
@@ -16,6 +16,7 @@ import scala.collection.mutable.ArrayBuffer
 
 case class DBusSimpleCmd() extends Bundle{
   val wr = Bool
+  val mask = Bits(4 bit)
   val address = UInt(32 bits)
   val data = Bits(32 bit)
   val size = UInt(2 bit)
@@ -441,6 +442,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
 
       //formal
       val formalMask = dBus.genMask(dBus.cmd)
+      dBus.cmd.mask := formalMask
 
       insert(FORMAL_MEM_ADDR) := dBus.cmd.address & U"xFFFFFFFC"
       insert(FORMAL_MEM_WMASK) := (dBus.cmd.valid &&  dBus.cmd.wr) ? formalMask | B"0000"