diff --git a/src/main/scala/vexriscv/demo/Linux.scala b/src/main/scala/vexriscv/demo/Linux.scala
index f7c9fe6..ff3fa0e 100644
--- a/src/main/scala/vexriscv/demo/Linux.scala
+++ b/src/main/scala/vexriscv/demo/Linux.scala
@@ -40,13 +40,13 @@ cd VexRiscv
 Run regressions =>
 sbt "runMain vexriscv.demo.LinuxGen -r"
 cd src/test/cpp/regression
-make run  IBUS=CACHED DBUS=SIMPLE DEBUG_PLUGIN=no DHRYSTONE=yes SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=10 TRACE=no
+make run  IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=no DHRYSTONE=yes SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=10 TRACE=no
 
 Run linux in simulation (Require the machime mode emulator compiled in SIM mode) =>
 sbt "runMain vexriscv.demo.LinuxGen"
 cd src/test/cpp/regression
 export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
-make run IBUS=CACHED DBUS=SIMPLE  DEBUG_PLUGIN=no SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/vmlinux.bin DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio TRACE=no FLOW_INFO=no
+make run IBUS=CACHED DBUS=CACHED  DEBUG_PLUGIN=no SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/vmlinux.bin DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio TRACE=no FLOW_INFO=no
 
 Run linux with QEMU (Require the machime mode emulator compiled in QEMU mode)
 export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
@@ -118,9 +118,9 @@ object LinuxGen {
           prediction = NONE,
           injectorStage = true,
           config = InstructionCacheConfig(
-            cacheSize = 4096,
+            cacheSize = 4096*2,
             bytePerLine = 32,
-            wayCount = 1,
+            wayCount = 2,
             addressWidth = 32,
             cpuDataWidth = 32,
             memDataWidth = 32,
@@ -147,9 +147,9 @@ object LinuxGen {
 //        ),
         new DBusCachedPlugin(
           config = new DataCacheConfig(
-            cacheSize         = 4096,
+            cacheSize         = 4096*2,
             bytePerLine       = 32,
-            wayCount          = 1,
+            wayCount          = 2,
             addressWidth      = 32,
             cpuDataWidth      = 32,
             memDataWidth      = 32,
diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
index e7bde27..55bd7df 100644
--- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -22,6 +22,10 @@ class DBusCachedPlugin(config : DataCacheConfig,
                        memoryTranslatorPortConfig : Any = null,
                        csrInfo : Boolean = false)  extends Plugin[VexRiscv] with DBusAccessService {
   import config._
+
+  assert(isPow2(cacheSize))
+  assert(!(memoryTranslatorPortConfig != null && config.cacheSize/config.wayCount > 4096), "When the D$ is used with MMU, each way can't be bigger than a page (4096 bytes)")
+
   var dBus  : DataCacheMemBus = null
   var mmuBus : MemoryTranslatorBus = null
   var exceptionBus : Flow[ExceptionCause] = null
diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
index ca74a0d..2b8c89c 100644
--- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
@@ -47,6 +47,10 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
   injectorStage = (!config.twoCycleCache && !withoutInjectorStage) || injectorStage){
   import config._
 
+  assert(isPow2(cacheSize))
+  assert(!(memoryTranslatorPortConfig != null && config.cacheSize/config.wayCount > 4096), "When the I$ is used with MMU, each way can't be bigger than a page (4096 bytes)")
+
+
   assert(!(withoutInjectorStage && injectorStage))
 
   var iBus  : InstructionCacheMemBus = null