From 41008551c16afaa3c1781db3f4623d01df5079d0 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Fri, 21 Feb 2020 20:01:35 +0100 Subject: [PATCH] CsrPlugin redo interface do not need next pc calculation --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 7d98bb9..8366b55 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -447,9 +447,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep if(supervisorGen) { - redoInterface = pcManagerService.createJumpInterface(pipeline.execute) - redoInterface.valid := False - redoInterface.payload.assignDontCare() + redoInterface = pcManagerService.createJumpInterface(pipeline.execute, -1) } exceptionPendings = Vec(Bool, pipeline.stages.length) @@ -643,10 +641,13 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep satpAccess(CSR.SATP, 31 -> satp.MODE, 22 -> satp.ASID, 0 -> satp.PPN) - if(supervisorGen) onWrite(CSR.SATP){ - execute.arbitration.flushNext := True - redoInterface.valid := True - redoInterface.payload := execute.input(PC) + 4 + if(supervisorGen) { + redoInterface.valid := False + redoInterface.payload := decode.input(PC) + onWrite(CSR.SATP){ + execute.arbitration.flushNext := True + redoInterface.valid := True + } } } }