From 41ea95f805f2213e14415a6b9642ea1c6ec78076 Mon Sep 17 00:00:00 2001
From: goekce <18174744+goekce@users.noreply.github.com>
Date: Thu, 14 Nov 2024 18:12:11 +0100
Subject: [PATCH] add argument for simulation frequency

---
 src/main/scala/vexriscv/demo/Murax.scala | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala
index 43e05e4..d7432b5 100644
--- a/src/main/scala/vexriscv/demo/Murax.scala
+++ b/src/main/scala/vexriscv/demo/Murax.scala
@@ -540,7 +540,10 @@ object MuraxWithRamInit{
 
 object MuraxWithRamInitWithNativeJtag{
   def main(args: Array[String]) {
-    SpinalVerilog(Murax(MuraxConfig.default.copy(withNativeJtag = true, onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")))
+    val coreFrequency = if (args.nonEmpty) HertzNumber(BigDecimal(args(0))) else MuraxConfig.default.coreFrequency
+    val (scaledValue, unit) = coreFrequency.decompose
+    println(s"coreFrequency = $scaledValue $unit")
+    SpinalVerilog(Murax(MuraxConfig.default.copy(coreFrequency=coreFrequency, withNativeJtag = true, onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")))
   }
 }