From 11cc9b1cf277df10886d8a6cae46e4a073a99154 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 2 Nov 2023 12:31:05 +0100 Subject: [PATCH 1/2] Add GenFullWithTcmIntegrated example --- README.md | 2 +- .../demo/GenFullWithTcmIntegrated.scala | 97 +++++++++++++++++++ 2 files changed, 98 insertions(+), 1 deletion(-) create mode 100644 src/main/scala/vexriscv/demo/GenFullWithTcmIntegrated.scala diff --git a/README.md b/README.md index 30c814e..165341f 100644 --- a/README.md +++ b/README.md @@ -72,7 +72,7 @@ This repository hosts a RISC-V implementation written in SpinalHDL. Here are som - Linux compatible (SoC : https://github.com/enjoy-digital/linux-on-litex-vexriscv) - Zephyr compatible - [FreeRTOS port](https://github.com/Dolu1990/FreeRTOS-RISCV) -- Support tightly coupled memory on I$ D$ (see GenFullWithTcm) +- Support tightly coupled memory on I$ D$ (see GenFullWithTcm / GenFullWithTcmIntegrated) The hardware description of this CPU is done by using a very software oriented approach (without any overhead in the generated hardware). Here is a list of software concepts used: diff --git a/src/main/scala/vexriscv/demo/GenFullWithTcmIntegrated.scala b/src/main/scala/vexriscv/demo/GenFullWithTcmIntegrated.scala new file mode 100644 index 0000000..4e68b5f --- /dev/null +++ b/src/main/scala/vexriscv/demo/GenFullWithTcmIntegrated.scala @@ -0,0 +1,97 @@ +package vexriscv.demo + +import spinal.core._ +import spinal.lib.bus.misc.SizeMapping +import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} +import vexriscv.plugin._ +import vexriscv.{VexRiscv, VexRiscvConfig, plugin} + +/** + * this example integrate the tightly coupled memory directly inside VexRiscv + * by using the IBusDBusCachedTightlyCoupledRam plugin + */ +object GenFullWithTcmIntegrated extends App{ + def config = VexRiscvConfig( + plugins = List( + new IBusDBusCachedTightlyCoupledRam( + mapping = SizeMapping(0x20000000, 0x1000) + ), + new IBusCachedPlugin( + prediction = DYNAMIC, + config = InstructionCacheConfig( + cacheSize = 4096, + bytePerLine =32, + wayCount = 1, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchIllegalAccess = true, + catchAccessFault = true, + asyncTagMemory = false, + twoCycleRam = true, + twoCycleCache = true + ), + memoryTranslatorPortConfig = MmuPortConfig( + portTlbSize = 4 + ) + ), + new DBusCachedPlugin( + config = new DataCacheConfig( + cacheSize = 4096, + bytePerLine = 32, + wayCount = 1, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchAccessError = true, + catchIllegal = true, + catchUnaligned = true + ), + memoryTranslatorPortConfig = MmuPortConfig( + portTlbSize = 6 + ) + ), + new MmuPlugin( + virtualRange = _(31 downto 28) === 0xC, + ioRange = _(31 downto 28) === 0xF + ), + new DecoderSimplePlugin( + catchIllegalInstruction = true + ), + new RegFilePlugin( + regFileReadyKind = plugin.SYNC, + zeroBoot = false + ), + new IntAluPlugin, + new SrcPlugin( + separatedAddSub = false, + executeInsertion = true + ), + new FullBarrelShifterPlugin, + new HazardSimplePlugin( + bypassExecute = true, + bypassMemory = true, + bypassWriteBack = true, + bypassWriteBackBuffer = true, + pessimisticUseSrc = false, + pessimisticWriteRegFile = false, + pessimisticAddressMatch = false + ), + new MulPlugin, + new DivPlugin, + new CsrPlugin(CsrPluginConfig.small(0x80000020l)), + new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), + new BranchPlugin( + earlyBranch = false, + catchAddressMisaligned = true + ), + new YamlPlugin("cpu0.yaml") + ) + ) + + def cpu() = new VexRiscv( + config + ) + + SpinalVerilog(cpu()) +} From e6998d1cb38518ab852b962fc3594ebd102b06b6 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 3 Nov 2023 10:46:49 +0100 Subject: [PATCH 2/2] Add GenFullWithOfficialRiscvDebug --- README.md | 2 + src/main/scala/vexriscv/TestsWorkspace.scala | 22 +-- .../demo/GenFullWithOfficialRiscvDebug.scala | 130 ++++++++++++++++++ 3 files changed, 143 insertions(+), 11 deletions(-) create mode 100644 src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala diff --git a/README.md b/README.md index 165341f..5de153e 100644 --- a/README.md +++ b/README.md @@ -1331,6 +1331,8 @@ init halt ``` +A full example can be found in GenFullWithOfficialRiscvDebug.scala + #### YamlPlugin This plugin offers a service to other plugins to generate a useful Yaml file describing the CPU configuration. It contains, for instance, the sequence of instructions required diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index df15a80..3938921 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -144,19 +144,19 @@ object TestsWorkspace { withDouble = true, externalFpu = false, simHalt = true, - privilegedDebug = false + privilegedDebug = true ) -// config.plugins += new EmbeddedRiscvJtag( -// p = DebugTransportModuleParameter( -// addressWidth = 7, -// version = 1, -// idle = 7 -// ), -// debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")), -// withTunneling = false, -// withTap = true -// ) + config.plugins += new EmbeddedRiscvJtag( + p = DebugTransportModuleParameter( + addressWidth = 7, + version = 1, + idle = 7 + ), + debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")), + withTunneling = false, + withTap = true + ) // l.foreach{ // case p : EmbeddedRiscvJtag => p.debugCd.load(ClockDomain.current.copy(reset = Bool().setName("debug_reset"))) diff --git a/src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala b/src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala new file mode 100644 index 0000000..663f907 --- /dev/null +++ b/src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala @@ -0,0 +1,130 @@ +package vexriscv.demo + +import spinal.core._ +import spinal.lib.cpu.riscv.debug.DebugTransportModuleParameter +import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} +import vexriscv.plugin._ +import vexriscv.{VexRiscv, VexRiscvConfig, plugin} + +/** + * This an example of VexRiscv configuration which can run the official RISC-V debug. + * You can for instance : + * - generate this VexRiscv + * - cd src/test/cpp/regression + * - make IBUS=CACHED IBUS_DATA_WIDTH=64 COMPRESSED=no DBUS=CACHED DBUS_LOAD_DATA_WIDTH=64 DBUS_STORE_DATA_WIDTH=64 LRSC=yes AMO=yes DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes MUL=yes DIV=yes SUPERVISOR=yes CSR=yes RVF=yes RVD=yes DEBUG_PLUGIN=RISCV WITH_RISCV_REF=no DEBUG_PLUGIN_EXTERNAL=yes DEBUG_PLUGIN=no VEXRISCV_JTAG=yes + * + * This will run a simulation of the CPU which wait for a tcp-jtag connection from openocd. + * That con connection can be done via openocd : + * - src/openocd -f config.tcl + * + * Were config.tcl is the following : + * + * ############################################## + * interface jtag_tcp + * adapter speed 5000 + * + * set _CHIPNAME riscv + * jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10002FFF + * + * set _TARGETNAME $_CHIPNAME.cpu + * + * target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME + * + * init + * halt + * + * echo "Ready for Remote Connections" + * ############################################## + */ + +object GenFullWithOfficialRiscvDebug extends App{ + def config = VexRiscvConfig( + plugins = List( + new IBusCachedPlugin( + prediction = DYNAMIC, + config = InstructionCacheConfig( + cacheSize = 4096, + bytePerLine =32, + wayCount = 1, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchIllegalAccess = true, + catchAccessFault = true, + asyncTagMemory = false, + twoCycleRam = true, + twoCycleCache = true + ), + memoryTranslatorPortConfig = MmuPortConfig( + portTlbSize = 4 + ) + ), + new DBusCachedPlugin( + config = new DataCacheConfig( + cacheSize = 4096, + bytePerLine = 32, + wayCount = 1, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchAccessError = true, + catchIllegal = true, + catchUnaligned = true + ), + memoryTranslatorPortConfig = MmuPortConfig( + portTlbSize = 6 + ) + ), + new MmuPlugin( + virtualRange = _(31 downto 28) === 0xC, + ioRange = _(31 downto 28) === 0xF + ), + new DecoderSimplePlugin( + catchIllegalInstruction = true + ), + new RegFilePlugin( + regFileReadyKind = plugin.SYNC, + zeroBoot = false + ), + new IntAluPlugin, + new SrcPlugin( + separatedAddSub = false, + executeInsertion = true + ), + new FullBarrelShifterPlugin, + new HazardSimplePlugin( + bypassExecute = true, + bypassMemory = true, + bypassWriteBack = true, + bypassWriteBackBuffer = true, + pessimisticUseSrc = false, + pessimisticWriteRegFile = false, + pessimisticAddressMatch = false + ), + new MulPlugin, + new DivPlugin, + new CsrPlugin(CsrPluginConfig.small(0x80000020l).copy(withPrivilegedDebug = true)), + new EmbeddedRiscvJtag( + p = DebugTransportModuleParameter( + addressWidth = 7, + version = 1, + idle = 7 + ), + debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")), + withTunneling = false, + withTap = true + ), + new BranchPlugin( + earlyBranch = false, + catchAddressMisaligned = true + ), + new YamlPlugin("cpu0.yaml") + ) + ) + + def cpu() = new VexRiscv(config){ + println(config.getRegressionArgs().mkString(" ")) + } + + SpinalVerilog(cpu()) +}