From 42bb1ab5910c2b43b28dd1e7bcb312ad2f4f4159 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Wed, 15 Sep 2021 11:36:51 +0200
Subject: [PATCH] d$ / i$ toWishbone bridges can now be bigger than 32 bits
 https://github.com/m-labs/VexRiscv-verilog/pull/12

---
 src/main/scala/vexriscv/ip/DataCache.scala        | 11 ++++++-----
 src/main/scala/vexriscv/ip/InstructionCache.scala | 10 +++++-----
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala
index e7bd199..ccf4803 100644
--- a/src/main/scala/vexriscv/ip/DataCache.scala
+++ b/src/main/scala/vexriscv/ip/DataCache.scala
@@ -77,9 +77,9 @@ case class DataCacheConfig(cacheSize : Int,
   )
 
   def getWishboneConfig() = WishboneConfig(
-    addressWidth = 30,
-    dataWidth = 32,
-    selWidth = 4,
+    addressWidth = 32-log2Up(memDataWidth/8),
+    dataWidth = memDataWidth,
+    selWidth = memDataBytes,
     useSTALL = false,
     useLOCK = false,
     useERR = true,
@@ -329,11 +329,12 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
     val wishboneConfig = p.getWishboneConfig()
     val bus = Wishbone(wishboneConfig)
     val counter = Reg(UInt(log2Up(p.burstSize) bits)) init(0)
+    val addressShift = log2Up(p.memDataWidth/8)
 
     val cmdBridge = Stream (DataCacheMemCmd(p))
     val isBurst = cmdBridge.isBurst
     cmdBridge.valid := cmd.valid
-    cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + 2) @@ counter @@ U"00") | (cmd.address(31 downto 2) @@ U"00"))
+    cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + addressShift) @@ counter @@ U(0, addressShift bits)) | (cmd.address(31 downto 2) @@ U(0, addressShift bits)))
     cmdBridge.wr := cmd.wr
     cmdBridge.mask := cmd.mask
     cmdBridge.data := cmd.data
@@ -353,7 +354,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
     bus.ADR := cmdBridge.address >> 2
     bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000")
     bus.BTE := B"00"
-    bus.SEL := cmdBridge.wr ? cmdBridge.mask | B"1111"
+    bus.SEL := cmdBridge.wr ? cmdBridge.mask | B((1 << p.memDataBytes)-1)
     bus.WE  := cmdBridge.wr
     bus.DAT_MOSI := cmdBridge.data
 
diff --git a/src/main/scala/vexriscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala
index ae8a80d..e09712c 100644
--- a/src/main/scala/vexriscv/ip/InstructionCache.scala
+++ b/src/main/scala/vexriscv/ip/InstructionCache.scala
@@ -56,9 +56,9 @@ case class InstructionCacheConfig( cacheSize : Int,
   )
 
   def getWishboneConfig() = WishboneConfig(
-    addressWidth = 30,
-    dataWidth = 32,
-    selWidth = 4,
+    addressWidth = 32-log2Up(memDataWidth/8),
+    dataWidth = memDataWidth,
+    selWidth = memDataWidth/8,
     useSTALL = false,
     useLOCK = false,
     useERR = true,
@@ -228,10 +228,10 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
     val pending = counter =/= 0
     val lastCycle = counter === counter.maxValue
 
-    bus.ADR := (cmd.address >> widthOf(counter) + 2) @@ counter
+    bus.ADR := (cmd.address >> widthOf(counter) + log2Up(p.memDataWidth/8)) @@ counter
     bus.CTI := lastCycle ? B"111" | B"010"
     bus.BTE := "00"
-    bus.SEL := "1111"
+    bus.SEL.setAll()
     bus.WE  := False
     bus.DAT_MOSI.assignDontCare()
     bus.CYC := False