From 455607b6b42909378ec12496b583aa6215b8bfc9 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 18 Apr 2018 14:11:59 +0200 Subject: [PATCH] Fix dBus IO access --- src/main/scala/vexriscv/ip/DataCache.scala | 4 ++-- src/test/cpp/regression/main.cpp | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala index bee154c..0963de1 100644 --- a/src/main/scala/vexriscv/ip/DataCache.scala +++ b/src/main/scala/vexriscv/ip/DataCache.scala @@ -307,8 +307,9 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave val counter = Reg(UInt(log2Up(p.burstSize) bits)) init(0) val cmdBridge = Stream (DataCacheMemCmd(p)) + val isBurst = cmdBridge.length =/= 0 cmdBridge.valid := cmd.valid - cmdBridge.address := (cmd.address >> widthOf(counter) + 2) @@ counter @@ "00" + cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + 2) @@ counter @@ "00") | (cmd.address(31 downto 2) @@ "00")) cmdBridge.wr := cmd.wr cmdBridge.mask := cmd.mask cmdBridge.data := cmd.data @@ -325,7 +326,6 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave } - val isBurst = cmdBridge.length =/= 0 bus.ADR := cmdBridge.address bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000") bus.BTE := "00" diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index f9634b9..7d9a0b8 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -430,8 +430,6 @@ public: top->eval(); - dump(i + 1); - if(top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_valid == 1 && top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_address != 0){ @@ -444,6 +442,8 @@ public: for(SimElement* simElement : simElements) simElement->preCycle(); + dump(i + 1); + if(withInstructionReadCheck){ if(top->VexRiscv->decode_arbitration_isValid && !top->VexRiscv->decode_arbitration_haltItself && !top->VexRiscv->decode_arbitration_flushAll){ uint32_t expectedData;