From 45ff78d0685aca501fbcdf23b8d91a8a2d73a38e Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 1 Dec 2020 13:51:03 +0100 Subject: [PATCH] VexRiscvSmpClusterGen.dBusCmdMasterPipe option added --- src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala index e067c39..83ac65a 100644 --- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala +++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala @@ -159,7 +159,8 @@ object VexRiscvSmpClusterGen { iCacheWays : Int = 2, dCacheWays : Int = 2, iBusRelax : Boolean = false, - earlyBranch : Boolean = false) = { + earlyBranch : Boolean = false, + dBusCmdMasterPipe : Boolean = false) = { assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes") assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes") val config = VexRiscvConfig( @@ -198,7 +199,7 @@ object VexRiscvSmpClusterGen { ) ), new DBusCachedPlugin( - dBusCmdMasterPipe = dBusWidth == 32, + dBusCmdMasterPipe = dBusCmdMasterPipe || dBusWidth == 32, dBusCmdSlavePipe = true, dBusRspSlavePipe = true, relaxedMemoryTranslationRegister = true,