From 47673863fb66ddc21e128361ac3a7ca1b66c2594 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 22 Feb 2021 19:27:55 +0100 Subject: [PATCH] fpu test cleaning --- src/test/scala/vexriscv/ip/fpu/FpuTest.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/test/scala/vexriscv/ip/fpu/FpuTest.scala b/src/test/scala/vexriscv/ip/fpu/FpuTest.scala index a0c97a0..dafac84 100644 --- a/src/test/scala/vexriscv/ip/fpu/FpuTest.scala +++ b/src/test/scala/vexriscv/ip/fpu/FpuTest.scala @@ -55,11 +55,11 @@ class FpuTest extends FunSuite{ } def testP(p : FpuParameter){ - val portCount = 1 + val portCount = 4 val config = SimConfig config.allOptimisation - if(p.withDouble) config.withFstWave +// if(p.withDouble) config.withFstWave config.compile(new FpuCore(portCount, p){ for(i <- 0 until portCount) out(Bits(5 bits)).setName(s"flagAcc$i") := io.port(i).completion.flags.asBits setDefinitionName("FpuCore"+ (if(p.withDouble) "Double" else ""))