From 485f35a1b5ffbf1a5823050ac4e812dfda13e739 Mon Sep 17 00:00:00 2001
From: Dolu1990 <papuchoud@hotmail.com>
Date: Thu, 24 May 2018 13:46:31 +0200
Subject: [PATCH] IBusCachedPlugin default is two cycle cache with single cycle
 ram.

---
 src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala | 2 +-
 src/main/scala/vexriscv/ip/InstructionCache.scala              | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala b/src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala
index c2ad233..124d235 100644
--- a/src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala
+++ b/src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala
@@ -29,7 +29,7 @@ object GenSmallAndProductiveICache extends App{
             catchMemoryTranslationMiss = false,
             asyncTagMemory = false,
             twoCycleRam = false,
-            twoCycleCache = false
+            twoCycleCache = true
           )
         ),
         new DBusSimplePlugin(
diff --git a/src/main/scala/vexriscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala
index e992d20..7892715 100644
--- a/src/main/scala/vexriscv/ip/InstructionCache.scala
+++ b/src/main/scala/vexriscv/ip/InstructionCache.scala
@@ -17,7 +17,7 @@ case class InstructionCacheConfig( cacheSize : Int,
                                    catchAccessFault : Boolean,
                                    catchMemoryTranslationMiss : Boolean,
                                    asyncTagMemory : Boolean,
-                                   twoCycleCache : Boolean = false,
+                                   twoCycleCache : Boolean = true,
                                    twoCycleRam : Boolean = false,
                                    preResetFlush : Boolean = false){