From 486d17d245594dc778001f24f5307ea2a00a9e1f Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 21 Oct 2022 18:58:13 +0200 Subject: [PATCH] CsrOpensbi now add rvc to misa --- src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala index dfc26b5..084d523 100644 --- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala +++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala @@ -201,8 +201,9 @@ object VexRiscvSmpClusterGen { assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes") assert(!(withDouble && !withFloat)) + val misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}${if(rvc) "c" else ""}${if(withSupervisor) "s" else ""}") val csrConfig = if(withSupervisor){ - CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}s")).copy(utimeAccess = CsrAccess.READ_ONLY, withPrivilegedDebug = privilegedDebug) + CsrPluginConfig.openSbi(mhartid = hartId, misa = misa).copy(utimeAccess = CsrAccess.READ_ONLY, withPrivilegedDebug = privilegedDebug) } else { CsrPluginConfig( catchIllegalAccess = true, @@ -210,7 +211,7 @@ object VexRiscvSmpClusterGen { marchid = null, mimpid = null, mhartid = hartId, - misaExtensionsInit = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}s"), + misaExtensionsInit = misa, misaAccess = if(forceMisa) CsrAccess.WRITE_ONLY else CsrAccess.NONE, mtvecAccess = CsrAccess.READ_WRITE, mtvecInit = null,