diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala
index af1c77b..b522aed 100644
--- a/src/main/scala/vexriscv/TestsWorkspace.scala
+++ b/src/main/scala/vexriscv/TestsWorkspace.scala
@@ -274,10 +274,3 @@ object TestsWorkspace {
     }
   }
 }
-
-//TODO DivPlugin should not used MixedDivider (double twoComplement)
-//TODO DivPlugin should register the twoComplement output before pipeline insertion
-//TODO MulPlugin doesn't fit well on Artix (FMAX)
-//TODO PcReg design is unoptimized by Artix synthesis
-//TODO FMAX SRC mux + bipass mux prioriti
-//TODO FMAX, isFiring is to pesimisstinc in some cases(include removeIt flushed ..)
\ No newline at end of file
diff --git a/src/main/scala/vexriscv/demo/smp/Misc.scala b/src/main/scala/vexriscv/demo/smp/Misc.scala
index b192a9c..9980cf4 100644
--- a/src/main/scala/vexriscv/demo/smp/Misc.scala
+++ b/src/main/scala/vexriscv/demo/smp/Misc.scala
@@ -188,7 +188,7 @@ case class BmbToLiteDram(bmbParameter : BmbParameter,
     wData.arbitrationFrom(dataFork.throwWhen(dataFork.isRead))
     wData.data := dataFork.data
     wData.we := dataFork.mask
-    io.output.wdata << wData.queueLowLatency(wdataFifoSize, latency = 1) //TODO queue low latency
+    io.output.wdata << wData.queueLowLatency(wdataFifoSize, latency = 1)
   } else {
     dataFork.ready := True
     io.output.wdata.valid := False
diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
index ccc1f57..efd4010 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
@@ -454,12 +454,9 @@ object VexRiscvSmpClusterTest extends App{
 // top -b -n 1
 
 // TODO
-// litex cluster should use out of order decoder
 // MultiChannelFifo.toStream arbitration
 // BmbDecoderOutOfOrder arbitration
 // DataCache to bmb invalidation that are more than single line
-// update fence w to w
-// DBusCachedPlugin dBusAccess execute.isValid := True is induce a longe combinatorial path to check conditions, D$ execute valid => execute haltIt
 object VexRiscvSmpClusterOpenSbi extends App{
   import spinal.core.sim._