From 4a40184b353c85a3d6fa491f427be5ea6cadf6ce Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Sat, 25 May 2019 00:22:27 +0200 Subject: [PATCH] Add cache Bandwidth counter, previous commit was about random instruction cache way allocation --- src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 8 ++++++++ src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala | 8 +++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index baf9ada..c981922 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -168,6 +168,14 @@ class DBusCachedPlugin(val config : DataCacheConfig, dBus.cmd << optionPipe(dBusCmdMasterPipe, cmdBuf)(_.m2sPipe()) cache.io.mem.rsp << optionPipe(dBusRspSlavePipe,dBus.rsp)(_.m2sPipe()) + pipeline plug new Area{ + //Memory bandwidth counter + val rspCounter = RegInit(UInt(32 bits)) init(0) + when(dBus.rsp.valid){ + rspCounter := rspCounter + 1 + } + } + decode plug new Area { import decode._ diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala index 362ac8d..4005fb9 100644 --- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala @@ -129,7 +129,13 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, iBus = master(new InstructionCacheMemBus(IBusCachedPlugin.this.config)).setName("iBus") iBus <> cache.io.mem iBus.cmd.address.allowOverride := cache.io.mem.cmd.address - + + //Memory bandwidth counter + val rspCounter = RegInit(UInt(32 bits)) init(0) + when(iBus.rsp.valid){ + rspCounter := rspCounter + 1 + } + val stageOffset = if(relaxedPcCalculation) 1 else 0 def stages = iBusRsp.stages.drop(stageOffset)