diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
index ad1d3c3..e691ea2 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
@@ -388,6 +388,10 @@ object VexRiscvSmpClusterTestInfrastructure{
       onWrite(PUTC)(data => print(data.toChar))
 //      onWrite(GETC)(data => System.in.read().toInt)
 
+      dut.io.softwareInterrupts #= 0
+      dut.io.timerInterrupts #= 0
+      dut.io.externalInterrupts #= 0
+      dut.io.externalSupervisorInterrupts #= 0
       onRead(CLINT_TIME_ADDR)(simTime().toInt)
       onRead(CLINT_TIME_ADDR+4)((simTime() >> 32).toInt)
       for(hartId <- 0 until cpuCount){
@@ -458,7 +462,7 @@ object VexRiscvSmpClusterOpenSbi extends App{
   simConfig.allOptimisation
   simConfig.addSimulatorFlag("--threads 1")
 
-  val cpuCount = 4
+  val cpuCount = 16
   val withStall = false
 
   simConfig.compile(VexRiscvSmpClusterGen.vexRiscvCluster(cpuCount)).doSimUntilVoid(seed = 42){dut =>