diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
index 5ed12f7..901e6d5 100644
--- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
@@ -379,7 +379,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
         when(enable){
           fetcher.haltIt()
         }
-        val done = ! List(decode, execute, memory, writeBack).map(_.arbitration.isValid).orR && fetcher.nextPc()._1
+        val done = ! List(execute, memory, writeBack).map(_.arbitration.isValid).orR && fetcher.nextPc()._1
 //        val done = History(doneAsync, 0 to 0).andR
       }
 
@@ -532,10 +532,9 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
       }
 
       //Manage WFI instructions
-      if(wfiGen) when(decode.arbitration.isValid && decode.input(ENV_CTRL) === EnvCtrlEnum.WFI){
+      if(wfiGen) when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.WFI){
         when(!interrupt){
-          fetcher.haltIt()
-          decode.arbitration.haltItself := True
+          execute.arbitration.haltItself := True
         }
       }
 
diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
index e21538e..03a0cc9 100644
--- a/src/main/scala/vexriscv/plugin/DebugPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
@@ -174,6 +174,7 @@ class DebugPlugin(val debugClockDomain : ClockDomain) extends Plugin[VexRiscv] w
           is(1) {
             when(io.bus.cmd.wr) {
               insertDecodeInstruction := True
+              //TODO !!!!
               decode.arbitration.isValid.getDrivingReg setWhen (firstCycle)
               decode.arbitration.haltItself setWhen (secondCycle)
               io.bus.cmd.ready := !firstCycle && !secondCycle && execute.arbitration.isValid
diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala
index cd3f282..98ace68 100644
--- a/src/main/scala/vexriscv/plugin/Fetcher.scala
+++ b/src/main/scala/vexriscv/plugin/Fetcher.scala
@@ -9,18 +9,17 @@ import scala.collection.mutable.ArrayBuffer
 
 
 
-abstract class IBusFetcherImpl(catchAccessFault : Boolean,
-                      pendingMax : Int = 7,
-                      resetVector : BigInt,
-                      keepPcPlus4 : Boolean,
-                      decodePcGen : Boolean,
-                      compressedGen : Boolean,
-                      cmdToRspStageCount : Int,
-                      rspStageGen : Boolean,
-                      injectorReadyCutGen : Boolean,
-                      relaxedPcCalculation : Boolean,
-                      prediction : BranchPrediction,
-                      catchAddressMisaligned : Boolean,
+abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
+                               val resetVector : BigInt,
+                               val keepPcPlus4 : Boolean,
+                               val decodePcGen : Boolean,
+                               val compressedGen : Boolean,
+                               val cmdToRspStageCount : Int,
+                               val rspStageGen : Boolean,
+                               val injectorReadyCutGen : Boolean,
+                               val relaxedPcCalculation : Boolean,
+                               val prediction : BranchPrediction,
+                               val catchAddressMisaligned : Boolean,
                       injectorStage : Boolean) extends Plugin[VexRiscv] with JumpService with IBusFetcher{
   var prefetchExceptionPort : Flow[ExceptionCause] = null
 
@@ -244,13 +243,12 @@ abstract class IBusFetcherImpl(catchAccessFault : Boolean,
     val injector = new Area {
       val inputBeforeHalt = condApply(if(decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(flush))
       val decodeInput = if(injectorStage){
-        val inputBeforeStage =  inputBeforeHalt.haltWhen(fetcherHalt)
-        val decodeInput = inputBeforeStage.m2sPipeWithFlush(killLastStage)
-        decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), inputBeforeStage.rsp.inst)
+        val decodeInput = inputBeforeHalt.m2sPipeWithFlush(killLastStage)
+        decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), inputBeforeHalt.rsp.inst)
         decodeInput
       } else {
         inputBeforeHalt
-      }
+      }.haltWhen(fetcherHalt)
 
       if(decodePcGen){
         decodeNextPcValid := True
diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
index ddcaa5f..3617353 100644
--- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
@@ -107,31 +107,18 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste
 
 class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean, pendingMax : Int = 7) extends IBusFetcherImpl(
     catchAccessFault = catchAccessFault,
-    pendingMax = 7,
     resetVector = BigInt(0x80000000l),
     keepPcPlus4 = false,
-    decodePcGen = false,
-    compressedGen = false,
+    decodePcGen = true,
+    compressedGen = true,
     cmdToRspStageCount = 1,
     rspStageGen = false,
     injectorReadyCutGen = false,
     relaxedPcCalculation = false,
     prediction = NONE,
-    catchAddressMisaligned = false,
+    catchAddressMisaligned = true,
     injectorStage = true){
   var iBus : IBusSimpleBus = null
-  def resetVector = BigInt(0x80000000l)
-  def keepPcPlus4 = false
-  def decodePcGen = false
-  def compressedGen = false
-  def cmdToRspStageCount = 1
-  def rspStageGen = false
-  def injectorReadyCutGen = false
-  def relaxedPcCalculation = false
-  def prediction : BranchPrediction = NONE
-  def catchAddressMisaligned = false
-  def injectorStage = true
-
 
   override def setup(pipeline: VexRiscv): Unit = {
     super.setup(pipeline)