From 960f8682ea5be8db3c1ef5bc03f9c7d2c4faacb0 Mon Sep 17 00:00:00 2001 From: StaubRobin Date: Mon, 25 Sep 2023 22:15:50 +0200 Subject: [PATCH] Add missing parameter jtagHeaderIgnoreWidth --- doc/nativeJtag/README.md | 4 ++-- src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/nativeJtag/README.md b/doc/nativeJtag/README.md index 550d8be..10c5b7e 100644 --- a/doc/nativeJtag/README.md +++ b/doc/nativeJtag/README.md @@ -49,7 +49,7 @@ as given could move with future changes to the file: ``` [254] val jtagCtrl = JtagTapInstructionCtrl() [255] val tap = jtagCtrl.fromXilinxBscane2(userId = 2) -[256] jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK)) +[256] jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK),0) ``` Changing the above lines, removes the Murax SoC’s JTAG ports as pins of the FPGA and inserts the BSCANE2 Xilinx Debug IP to which the JTAG signals are now connected. @@ -84,7 +84,7 @@ in e.g. the path: `project_name.srcs\sources_1\imports\Downloads` [44] wire tesic_tdo; [45] reg soc_tck,soc_tms,soc_tdi; [46] wire soc_tdo; -[47] +[47] [48] always @(*) begin [49] {soc_tck, soc_tms, soc_tdi } = {tck,tms,tdi}; [50] tdo = soc_tdo; diff --git a/src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala b/src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala index f817fb3..8a49a27 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala @@ -168,7 +168,7 @@ object VexRiscvAhbLite3{ // // On Artix FPGA jtag : // val jtagCtrl = JtagTapInstructionCtrl() // val tap = jtagCtrl.fromXilinxBscane2(userId = 1) -// jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK)) +// jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK),0) } case _ => }