From 4ed4af6a3e0089eadc980fae615102ac9665432c Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 24 Oct 2018 01:28:37 +0200 Subject: [PATCH] SrcPlugin add decodeAddSub option --- src/main/scala/vexriscv/plugin/SrcPlugin.scala | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/SrcPlugin.scala b/src/main/scala/vexriscv/plugin/SrcPlugin.scala index d319b9b..395c0a7 100644 --- a/src/main/scala/vexriscv/plugin/SrcPlugin.scala +++ b/src/main/scala/vexriscv/plugin/SrcPlugin.scala @@ -4,7 +4,7 @@ import vexriscv.{RVC_GEN, Riscv, VexRiscv} import spinal.core._ -class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false) extends Plugin[VexRiscv]{ +class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false, decodeAddSub : Boolean = false) extends Plugin[VexRiscv]{ override def build(pipeline: VexRiscv): Unit = { import pipeline._ import pipeline.config._ @@ -27,9 +27,10 @@ class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = ) } + val addSubStage = if(decodeAddSub) decode else execute if(separatedAddSub) { - execute plug new Area { - import execute._ + addSubStage plug new Area { + import addSubStage._ // ADD, SUB val add = (input(SRC1).asUInt + input(SRC2).asUInt).asBits.addAttribute("keep") @@ -45,8 +46,8 @@ class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = insert(SRC_LESS) := less } }else{ - execute plug new Area { - import execute._ + addSubStage plug new Area { + import addSubStage._ // ADD, SUB val addSub = (input(SRC1).asSInt + Mux(input(SRC_USE_SUB_LESS), ~input(SRC2), input(SRC2)).asSInt + Mux(input(SRC_USE_SUB_LESS), S(1), S(0))).asBits