diff --git a/src/main/scala/vexriscv/plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala
index 46e2897..0c1dd0b 100644
--- a/src/main/scala/vexriscv/plugin/BranchPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala
@@ -55,6 +55,7 @@ class BranchPlugin(earlyBranch : Boolean,
                    fenceiGenAsAJump : Boolean = false,
                    fenceiGenAsANop : Boolean = false) extends Plugin[VexRiscv] with PredictionInterface{
 
+
   def catchAddressMisalignedForReal = catchAddressMisaligned && !pipeline(RVC_GEN)
   lazy val branchStage = if(earlyBranch) pipeline.execute else pipeline.memory
 
@@ -88,6 +89,8 @@ class BranchPlugin(earlyBranch : Boolean,
     import pipeline.config._
     import IntAluPlugin._
 
+    assert(earlyBranch || withMemoryStage, "earlyBranch must be true when memory stage is disabled!")
+
     val bActions = List[(Stageable[_ <: BaseType],Any)](
       SRC1_CTRL         -> Src1CtrlEnum.RS,
       SRC2_CTRL         -> Src2CtrlEnum.RS,
@@ -375,4 +378,4 @@ class BranchPlugin(earlyBranch : Boolean,
       }
     }
   }
-}
\ No newline at end of file
+}