From 4fff62d3feeb05edcea46e66b25de0ecf3f274fa Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Wed, 11 May 2022 14:10:11 +0200
Subject: [PATCH] Fix RVC step by step triggering next instruction branch
 predictor

---
 src/main/scala/vexriscv/Services.scala           | 1 +
 src/main/scala/vexriscv/plugin/DebugPlugin.scala | 4 ++++
 src/main/scala/vexriscv/plugin/Fetcher.scala     | 6 ++++++
 3 files changed, 11 insertions(+)

diff --git a/src/main/scala/vexriscv/Services.scala b/src/main/scala/vexriscv/Services.scala
index 8a291d6..140c69b 100644
--- a/src/main/scala/vexriscv/Services.scala
+++ b/src/main/scala/vexriscv/Services.scala
@@ -17,6 +17,7 @@ trait IBusFetcher{
   def pcValid(stage : Stage) : Bool
   def getInjectionPort() : Stream[Bits]
   def withRvc() : Boolean
+  def forceNoDecode() : Unit
 }
 
 
diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
index 87d4f56..a0b4619 100644
--- a/src/main/scala/vexriscv/plugin/DebugPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
@@ -319,6 +319,10 @@ class DebugPlugin(var debugClockDomain : ClockDomain, hardwareBreakpointCount :
       if(pipeline.config.withRvc){
         val cleanStep = RegNext(stepIt && decode.arbitration.isFiring) init(False)
         execute.arbitration.flushNext setWhen(cleanStep)
+        when(cleanStep){
+          execute.arbitration.flushNext := True
+          iBusFetcher.forceNoDecode()
+        }
       }
 
       io.resetOut := RegNext(resetIt)
diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala
index 8b276e1..fdfde8b 100644
--- a/src/main/scala/vexriscv/plugin/Fetcher.scala
+++ b/src/main/scala/vexriscv/plugin/Fetcher.scala
@@ -33,6 +33,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
 //  assert(!(cmdToRspStageCount == 1 && !injectorStage))
   assert(!(compressedGen && !decodePcGen))
   var fetcherHalt : Bool = null
+  var forceNoDecodeCond : Bool = null
   var pcValids : Vec[Bool] = null
   def pcValid(stage : Stage) = pcValids(pipeline.indexOf(stage))
   var incomingInstruction : Bool = null
@@ -50,6 +51,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
   var predictionJumpInterface : Flow[UInt] = null
 
   override def haltIt(): Unit = fetcherHalt := True
+  override def forceNoDecode(): Unit = forceNoDecodeCond := True
   case class JumpInfo(interface :  Flow[UInt], stage: Stage, priority : Int)
   val jumpInfos = ArrayBuffer[JumpInfo]()
   override def createJumpInterface(stage: Stage, priority : Int = 0): Flow[UInt] = {
@@ -63,6 +65,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
 //  var decodeExceptionPort : Flow[ExceptionCause] = null
   override def setup(pipeline: VexRiscv): Unit = {
     fetcherHalt = False
+    forceNoDecodeCond = False
     incomingInstruction = False
     if(resetVector == null) externalResetVector = in(UInt(32 bits).setName("externalResetVector"))
 
@@ -408,6 +411,9 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
         })
       }
 
+      Component.current.addPrePopTask(() => {
+        decode.arbitration.isValid clearWhen(forceNoDecodeCond)
+      })
 
       //Formal verification signals generation, miss prediction stuff ?
       val formal = new Area {