From 5190ba28e0dd7be9ab7ef10cf2e37ced2b6d8381 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 16 Jul 2017 19:06:05 +0200 Subject: [PATCH] readme add features --- README.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 7856368..46fcce6 100644 --- a/README.md +++ b/README.md @@ -16,14 +16,15 @@ This repository host an RISC-V implementation written in SpinalHDL. There is some specs : - RV32IM instruction set -- Interrupts and exception handling with the Machine mode from the riscv-privileged-v1.9.1 specification. - Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack) - 1.16 DMIPS/Mhz when all features are enabled extension - Optimized for FPGA -- Optional MUL/DIV/REM extension +- Optional MUL/DIV extension - Optional instruction and data caches - Optional MMU -- Two implementation of shift instructions, Single cycle / shiftNumber cycle +- Optional debug extension allowing GDB debugging via an openOCD JTAG connection +- Optional interrupts and exception handling with the Machine and the User mode from the riscv-privileged-v1.9.1 spec. +- Two implementation of shift instructions, Single cycle / shiftNumber cycles - Each stage could have bypass or interlock hazard logic - FreeRTOS port https://github.com/Dolu1990/FreeRTOS-RISCV