diff --git a/src/main/scala/vexriscv/demo/MuraxUtiles.scala b/src/main/scala/vexriscv/demo/MuraxUtiles.scala
index e9be653..b940e8c 100644
--- a/src/main/scala/vexriscv/demo/MuraxUtiles.scala
+++ b/src/main/scala/vexriscv/demo/MuraxUtiles.scala
@@ -52,7 +52,7 @@ class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{
 }
 
 
-class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpleBusConfig : SimpleBusConfig) extends Component{
+case class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpleBusConfig : SimpleBusConfig) extends Component{
   val io = new Bundle{
     val bus = slave(SimpleBus(simpleBusConfig))
   }
diff --git a/src/main/scala/vexriscv/demo/SimpleBus.scala b/src/main/scala/vexriscv/demo/SimpleBus.scala
index 923259c..73eee31 100644
--- a/src/main/scala/vexriscv/demo/SimpleBus.scala
+++ b/src/main/scala/vexriscv/demo/SimpleBus.scala
@@ -271,7 +271,15 @@ case class SimpleBusInterconnect(){
     }
 
     for(connection <- connections){
-      connection.connector(connectionsInput(connection), connectionsOutput(connection))
+      val m = connectionsInput(connection)
+      val s = connectionsOutput(connection)
+      if(m.config == s.config) {
+        connection.connector(m, s)
+      }else{
+        val tmp = cloneOf(s)
+        m >> tmp //Adapte the bus kind.
+        connection.connector(tmp,s)
+      }
     }
   }