From 54412bde30af4d27625e8fe77b8e93dcabde5cc7 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Thu, 21 Jul 2022 09:10:23 +0200
Subject: [PATCH] getDrivingReg() update

---
 src/main/scala/vexriscv/Stage.scala                   | 2 +-
 src/main/scala/vexriscv/ip/fpu/FpuCore.scala          | 4 ++--
 src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 6 +++---
 src/main/scala/vexriscv/plugin/Fetcher.scala          | 2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/vexriscv/Stage.scala b/src/main/scala/vexriscv/Stage.scala
index fe20d19..5275622 100644
--- a/src/main/scala/vexriscv/Stage.scala
+++ b/src/main/scala/vexriscv/Stage.scala
@@ -75,5 +75,5 @@ class Stage() extends Area{
     dontSample.getOrElseUpdate(s, ArrayBuffer[Bool]()) += cond
   }
   def inputInit[T <: BaseType](stageable : Stageable[T],initValue : T) =
-    Component.current.addPrePopTask(() => inputsDefault(stageable.asInstanceOf[Stageable[Data]]).asInstanceOf[T].getDrivingReg.init(initValue))
+    Component.current.addPrePopTask(() => inputsDefault(stageable.asInstanceOf[Stageable[Data]]).asInstanceOf[T].getDrivingReg().init(initValue))
 }
\ No newline at end of file
diff --git a/src/main/scala/vexriscv/ip/fpu/FpuCore.scala b/src/main/scala/vexriscv/ip/fpu/FpuCore.scala
index 657b2fb..a9e9959 100644
--- a/src/main/scala/vexriscv/ip/fpu/FpuCore.scala
+++ b/src/main/scala/vexriscv/ip/fpu/FpuCore.scala
@@ -530,7 +530,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
           busy := True
           when(boot){
             when(input.i2f && !patched && input.value(31) && input.arg(0)){
-              input.value.getDrivingReg(0, 32 bits) := B(input.value.asUInt.twoComplement(True).resize(32 bits))
+              input.value.getDrivingReg()(0, 32 bits) := B(input.value.asUInt.twoComplement(True).resize(32 bits))
               patched := True
             } otherwise {
               shift.by := OHToUInt(OHMasking.first((ohInput).reversed))
@@ -1318,7 +1318,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
       is(_15_XYY2){
         when(mulBuffer.valid) {
           state := Y_15_XYY2
-          mulBuffer.payload.getDrivingReg := (U"11" << mulWidth-2) - (mulBuffer.payload)
+          mulBuffer.payload.getDrivingReg() := (U"11" << mulWidth-2) - (mulBuffer.payload)
         }
       }
       is(Y_15_XYY2){
diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
index 80d4409..50b953e 100644
--- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -371,7 +371,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
         insert(MEMORY_VIRTUAL_ADDRESS) := cache.io.cpu.execute.address
         memory.input(MEMORY_VIRTUAL_ADDRESS)
         if(writeBack != null) addPrePopTask( () =>
-          KeepAttribute(memory.input(MEMORY_VIRTUAL_ADDRESS).getDrivingReg)
+          KeepAttribute(memory.input(MEMORY_VIRTUAL_ADDRESS).getDrivingReg())
         )
       }
     }
@@ -528,14 +528,14 @@ class DBusCachedPlugin(val config : DataCacheConfig,
       dBusAccess.rsp.error := cache.io.cpu.writeBack.unalignedAccess || cache.io.cpu.writeBack.accessError
       dBusAccess.rsp.redo := cache.io.cpu.redo
       component.addPrePopTask{() =>
-        managementStage.input(IS_DBUS_SHARING).getDrivingReg clearWhen(dBusAccess.rsp.fire)
+        managementStage.input(IS_DBUS_SHARING).getDrivingReg() clearWhen(dBusAccess.rsp.fire)
         when(forceDatapath){
           execute.output(REGFILE_WRITE_DATA) := dBusAccess.cmd.address.asBits
         }
         if(mmuAndBufferStage != execute) mmuAndBufferStage.input(IS_DBUS_SHARING) init(False)
         managementStage.input(IS_DBUS_SHARING) init(False)
         when(dBusAccess.rsp.valid){
-          managementStage.input(IS_DBUS_SHARING).getDrivingReg := False
+          managementStage.input(IS_DBUS_SHARING).getDrivingReg() := False
         }
       }
     }
diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala
index 14450a1..f793084 100644
--- a/src/main/scala/vexriscv/plugin/Fetcher.scala
+++ b/src/main/scala/vexriscv/plugin/Fetcher.scala
@@ -390,7 +390,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
 
           //Check if the decode instruction is driven by a register
           val instructionDriver = try {
-            decode.input(INSTRUCTION).getDrivingReg
+            decode.input(INSTRUCTION).getDrivingReg()
           } catch {
             case _: Throwable => null
           }