From 5704f22739e854a85fb01c8873e4e33364a77dae Mon Sep 17 00:00:00 2001
From: Dolu1990 <papuchoud@hotmail.com>
Date: Sun, 27 May 2018 23:33:57 +0200
Subject: [PATCH] wip

---
 src/main/scala/vexriscv/TestsWorkspace.scala | 2 +-
 src/main/scala/vexriscv/plugin/Fetcher.scala | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala
index c381b4f..51d57d3 100644
--- a/src/main/scala/vexriscv/TestsWorkspace.scala
+++ b/src/main/scala/vexriscv/TestsWorkspace.scala
@@ -37,7 +37,7 @@ object TestsWorkspace {
             prediction = DYNAMIC,
             historyRamSizeLog2 = 8,
             catchAccessFault = true,
-            compressedGen = false
+            compressedGen = true
           ),
 //          new IBusCachedPlugin(
 //            resetVector = 0x80000000l,
diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala
index dfe5f54..1fece16 100644
--- a/src/main/scala/vexriscv/plugin/Fetcher.scala
+++ b/src/main/scala/vexriscv/plugin/Fetcher.scala
@@ -488,7 +488,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
 
 
         historyWrite.valid := False
-        historyWrite.address := (branchStage.input(PC) >> 2).resized
+        historyWrite.address := branchStage.input(PC)(2, historyRamSizeLog2 bits)
         historyWrite.data.source := branchStage.input(PC).asBits >> 1 + historyRamSizeLog2
         historyWrite.data.target := fetchPrediction.rsp.finalPc