From 68e704f3092be640aa92c876cf78702a83167f94 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 2 Sep 2021 15:42:33 +0200 Subject: [PATCH 1/5] restore avalon d$ tests --- src/test/cpp/regression/main.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 82cc4d3..4d9f2b8 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -2747,8 +2747,10 @@ public: virtual void preCycle(){ if ((top->dBusAvalon_read || top->dBusAvalon_write) && top->dBusAvalon_waitRequestn) { if(top->dBusAvalon_write){ + uint32_t size = __builtin_popcount(top->dBusAvalon_byteEnable); + uint32_t offset = ffs(top->dBusAvalon_byteEnable)-1; bool error_next = false; - ws->dBusAccess(top->dBusAvalon_address + beatCounter * 4,1,2,top->dBusAvalon_byteEnable,&top->dBusAvalon_writeData,&error_next); + ws->dBusAccess(top->dBusAvalon_address + beatCounter * 4 + offset,1,size,((uint8_t*)&top->dBusAvalon_writeData)+offset,&error_next); beatCounter++; if(beatCounter == top->dBusAvalon_burstCount){ beatCounter = 0; @@ -2756,7 +2758,7 @@ public: } else { for(int beat = 0;beat < top->dBusAvalon_burstCount;beat++){ DBusCachedAvalonTask rsp; - ws->dBusAccess(top->dBusAvalon_address + beat * 4,0,2,0,&rsp.data,&rsp.error); + ws->dBusAccess(top->dBusAvalon_address + beat * 4 ,0,4,((uint8_t*)&rsp.data),&rsp.error); rsps.push(rsp); } } From 53a333034092159a6d726acfb5e1c2d0443f7f04 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 18 Dec 2021 09:10:43 +0100 Subject: [PATCH 2/5] Update build.properties --- project/build.properties | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/project/build.properties b/project/build.properties index 72f9028..0b2e09c 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.2.7 +sbt.version=1.4.7 From 4824827b7ed6331acfda1c2b0dd8c9fb7361cb96 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 20 Dec 2021 09:38:02 +0100 Subject: [PATCH 3/5] Enable scala 2.13 compatibility --- .../scala/spinal/lib/eda/icestorm/IcestormFlow.scala | 2 ++ src/main/scala/vexriscv/VexRiscv.scala | 9 +++++---- src/main/scala/vexriscv/demo/Briey.scala | 2 +- src/main/scala/vexriscv/demo/Murax.scala | 5 +++-- 4 files changed, 11 insertions(+), 7 deletions(-) diff --git a/src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala b/src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala index b6ab7b5..6ef8d08 100644 --- a/src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala +++ b/src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala @@ -13,6 +13,8 @@ import spinal.lib.eda.bench.Report import scala.sys.process._ +import scala.collection.Seq + object IcestormFlow { def doCmd(cmd : Seq[String], path : String): String ={ println(cmd) diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala index 2bc647d..d3feda3 100644 --- a/src/main/scala/vexriscv/VexRiscv.scala +++ b/src/main/scala/vexriscv/VexRiscv.scala @@ -4,6 +4,7 @@ import vexriscv.plugin._ import spinal.core._ import scala.collection.mutable.ArrayBuffer +import scala.collection.Seq object VexRiscvConfig{ def apply(withMemoryStage : Boolean, withWriteBackStage : Boolean, plugins : Seq[Plugin[VexRiscv]]): VexRiscvConfig = { @@ -135,10 +136,10 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{ plugins ++= config.plugins //regression usage - val lastStageInstruction = CombInit(stages.last.input(config.INSTRUCTION)) keep() addAttribute (Verilator.public) - val lastStagePc = CombInit(stages.last.input(config.PC)) keep() addAttribute (Verilator.public) - val lastStageIsValid = CombInit(stages.last.arbitration.isValid) keep() addAttribute (Verilator.public) - val lastStageIsFiring = CombInit(stages.last.arbitration.isFiring) keep() addAttribute (Verilator.public) + val lastStageInstruction = CombInit(stages.last.input(config.INSTRUCTION)).keep().addAttribute (Verilator.public) + val lastStagePc = CombInit(stages.last.input(config.PC)).keep().addAttribute(Verilator.public) + val lastStageIsValid = CombInit(stages.last.arbitration.isValid).keep().addAttribute(Verilator.public) + val lastStageIsFiring = CombInit(stages.last.arbitration.isFiring).keep().addAttribute(Verilator.public) //Verilator perf decode.arbitration.removeIt.noBackendCombMerge diff --git a/src/main/scala/vexriscv/demo/Briey.scala b/src/main/scala/vexriscv/demo/Briey.scala index 701af7b..32e6d62 100644 --- a/src/main/scala/vexriscv/demo/Briey.scala +++ b/src/main/scala/vexriscv/demo/Briey.scala @@ -24,7 +24,7 @@ import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal} import spinal.lib.system.debugger.{JtagAxi4SharedDebugger, JtagBridge, SystemDebugger, SystemDebuggerConfig} import scala.collection.mutable.ArrayBuffer - +import scala.collection.Seq case class BrieyConfig(axiFrequency : HertzNumber, onChipRamSize : BigInt, diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 05c8e00..7c679a1 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -16,6 +16,7 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin} import spinal.lib.com.spi.ddr._ import spinal.lib.bus.simple._ import scala.collection.mutable.ArrayBuffer +import scala.collection.Seq /** * Created by PIC32F_USER on 28/07/2017. @@ -313,13 +314,13 @@ case class Murax(config : MuraxConfig) extends Component{ //******** Memory mappings ********* val apbDecoder = Apb3Decoder( master = apbBridge.io.apb, - slaves = apbMapping + slaves = apbMapping.toSeq ) val mainBusDecoder = new Area { val logic = new MuraxPipelinedMemoryBusDecoder( master = mainBusArbiter.io.masterBus, - specification = mainBusMapping, + specification = mainBusMapping.toSeq, pipelineMaster = pipelineMainBus ) } From fe6c391fe434b36733b7819471060d0d459207f4 Mon Sep 17 00:00:00 2001 From: Oscar Shiang Date: Tue, 4 Jan 2022 16:31:23 +0800 Subject: [PATCH 4/5] Fix typo in Linux.scala Correct "machime" to "machine". --- src/main/scala/vexriscv/demo/Linux.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/demo/Linux.scala b/src/main/scala/vexriscv/demo/Linux.scala index 0010fa3..8508a67 100644 --- a/src/main/scala/vexriscv/demo/Linux.scala +++ b/src/main/scala/vexriscv/demo/Linux.scala @@ -42,13 +42,13 @@ sbt "runMain vexriscv.demo.LinuxGen -r" cd src/test/cpp/regression make clean run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes MMU=yes CSR=yes DEBUG_PLUGIN=no COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes REDO=10 TRACE=no COREMARK=yes LINUX_REGRESSION=yes -Run linux in simulation (Require the machime mode emulator compiled in SIM mode) => +Run linux in simulation (Require the machine mode emulator compiled in SIM mode) => sbt "runMain vexriscv.demo.LinuxGen" cd src/test/cpp/regression export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal make clean run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes DEBUG_PLUGIN=no COMPRESSED=no LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/Image DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio WITH_USER_IO=yes TRACE=no FLOW_INFO=no -Run linux with QEMU (Require the machime mode emulator compiled in QEMU mode) +Run linux with QEMU (Require the machine mode emulator compiled in QEMU mode) export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal qemu-system-riscv32 -nographic -machine virt -m 1536M -device loader,file=src/main/c/emulator/build/emulator.bin,addr=0x80000000,cpu-num=0 -device loader,file=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb,addr=0xC3000000 -device loader,file=$BUILDROOT/output/images/Image,addr=0xC0000000 -device loader,file=$BUILDROOT/output/images/rootfs.cpio,addr=0xc2000000 From 57dd80a5667af6e06f8f7886abefd16d70749d9f Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Wed, 26 Jan 2022 08:59:03 +0100 Subject: [PATCH 5/5] plugin: CsrPlugin: Init cycle and instret registers Both counters are initialized with "randBoot()". This is fine for FPGA designs because the registers can be loaded with default values but ASIC designs require to load the value during a reset. Since both counters require to start at 0 (read-only CSR registers), change both registers from "randBoot()" to "init(0)". Error: reg [63:0] CsrPlugin_mcycle = 64'b0000000...00000000000; | Warning : Ignoring unsynthesizable construct. [VLOGPT-37] Signed-off-by: Daniel Schultz --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 60d1b34..bd48928 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -689,8 +689,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep val exceptionCode = Reg(UInt(trapCodeWidth bits)) } val mtval = Reg(UInt(xlen bits)) - val mcycle = Reg(UInt(64 bits)) randBoot() - val minstret = Reg(UInt(64 bits)) randBoot() + val mcycle = Reg(UInt(64 bits)) init(0) + val minstret = Reg(UInt(64 bits)) init(0) val medeleg = supervisorGen generate new Area {