From 57dd80a5667af6e06f8f7886abefd16d70749d9f Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Wed, 26 Jan 2022 08:59:03 +0100 Subject: [PATCH] plugin: CsrPlugin: Init cycle and instret registers Both counters are initialized with "randBoot()". This is fine for FPGA designs because the registers can be loaded with default values but ASIC designs require to load the value during a reset. Since both counters require to start at 0 (read-only CSR registers), change both registers from "randBoot()" to "init(0)". Error: reg [63:0] CsrPlugin_mcycle = 64'b0000000...00000000000; | Warning : Ignoring unsynthesizable construct. [VLOGPT-37] Signed-off-by: Daniel Schultz --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 60d1b34..bd48928 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -689,8 +689,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep val exceptionCode = Reg(UInt(trapCodeWidth bits)) } val mtval = Reg(UInt(xlen bits)) - val mcycle = Reg(UInt(64 bits)) randBoot() - val minstret = Reg(UInt(64 bits)) randBoot() + val mcycle = Reg(UInt(64 bits)) init(0) + val minstret = Reg(UInt(64 bits)) init(0) val medeleg = supervisorGen generate new Area {