diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
index 9281ceb..bdd60f1 100644
--- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -4,8 +4,19 @@ import vexriscv.ip._
 import vexriscv._
 import spinal.core._
 import spinal.lib._
+import spinal.lib.bus.amba4.axi.Axi4
 
 
+class DAxiCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : Any = null) extends DBusCachedPlugin(config, memoryTranslatorPortConfig){
+  var dAxi  : Axi4 = null
+
+  override def build(pipeline: VexRiscv): Unit = {
+    super.build(pipeline)
+    dBus.asDirectionLess()
+    dAxi = master(dBus.toAxi4Shared().toAxi4()).setName("dAxi")
+    dBus = null //For safety, as nobody should use it anymore :)
+  }
+}
 
 class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : Any = null)  extends Plugin[VexRiscv]{
   import config._
diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
index 2a3b959..cec4c6e 100644
--- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
@@ -103,6 +103,8 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
     axi2
   }
 
+  def toAxi4(stageCmd : Boolean = true) = this.toAxi4Shared(stageCmd).toAxi4()
+
 
 
   def toAvalon(stageCmd : Boolean = true): AvalonMM = {