diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala
index fb19cce..b1be18a 100644
--- a/src/main/scala/vexriscv/demo/SynthesisBench.scala
+++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala
@@ -20,7 +20,6 @@ object VexRiscvSynthesisBench {
       SpinalVerilog(GenSmallest.cpu().setDefinitionName(getRtlPath().split("\\.").head))
     }
 
-
     val smallAndProductive = new Rtl {
       override def getName(): String = "VexRiscv small and productive"
       override def getRtlPath(): String = "VexRiscvSmallAndProductive.v"
@@ -33,7 +32,6 @@ object VexRiscvSynthesisBench {
       SpinalVerilog(GenFullNoMmuNoCache.cpu().setDefinitionName(getRtlPath().split("\\.").head))
     }
 
-
     val fullNoMmu = new Rtl {
       override def getName(): String = "VexRiscv full no MMU"
       override def getRtlPath(): String = "VexRiscvFullNoMmu.v"
@@ -105,8 +103,22 @@ object MuraxSynthesisBench {
     }
 
 
+    val muraxFast = new Rtl {
+      override def getName(): String = "MuraxFast"
+      override def getRtlPath(): String = "MuraxFast.v"
+      SpinalVerilog({
+        val murax = new Murax(MuraxConfig.default.copy(
+          bypassExecute         = true,
+          bypassMemory          = true,
+          bypassWriteBack       = true,
+          bypassWriteBackBuffer = true
+        )).setDefinitionName(getRtlPath().split("\\.").head)
+        murax.io.mainClk.setName("clk")
+        murax
+      })
+    }
 
-    val rtls = List(murax)
+    val rtls = List(murax, muraxFast)
 
     val targets = XilinxStdTargets(
       vivadoArtix7Path = "E:\\Xilinx\\Vivado\\2016.3\\bin"