From 5c594d6d2ad5b0ab4874ab1e4d8f891b92b02e87 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Fri, 7 Apr 2017 13:27:47 +0200 Subject: [PATCH] IBusCachedPlugin move memory access outside the pipeline --- .../SpinalRiscv/Plugin/IBusCachedPlugin.scala | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala b/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala index aef97a4..7763575 100644 --- a/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala +++ b/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala @@ -200,10 +200,6 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{ })) - if(wrappedMemAccess) - io.mem.cmd.address := requestIn.addr(tagRange.high downto wordRange.low) @@ U(0,wordRange.low bit) - else - io.mem.cmd.address := requestIn.addr(tagRange.high downto lineRange.low) @@ U(0,lineRange.low bit) val flushCounter = Reg(UInt(log2Up(wayLineCount) + 1 bit)) init(0) @@ -231,15 +227,21 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{ - val request = requestIn.haltWhen(!io.mem.cmd.ready).stage() + val request = requestIn.stage() val lineInfoWrite = new LineInfo() lineInfoWrite.valid := flushCounter.msb lineInfoWrite.address := request.addr(tagRange) if(catchAccessFault) lineInfoWrite.error := loadingWithError + //Send memory requests + val memCmdSended = RegInit(False) setWhen(io.mem.cmd.fire) + io.mem.cmd.valid := request.valid && !memCmdSended + if(wrappedMemAccess) + io.mem.cmd.address := request.addr(tagRange.high downto wordRange.low) @@ U(0,wordRange.low bit) + else + io.mem.cmd.address := request.addr(tagRange.high downto lineRange.low) @@ U(0,lineRange.low bit) - io.mem.cmd.valid := requestIn.valid && !request.isStall val wordIndex = Reg(UInt(log2Up(wordPerLine) bit)) val loadedWordsNext = Bits(wordPerLine bit) val loadedWords = RegNext(loadedWordsNext) @@ -267,7 +269,8 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{ } when(requestIn.ready){ - wordIndex := io.mem.cmd.address(wordRange) + memCmdSended := False + wordIndex := requestIn.addr(wordRange) loadedWords := 0 loadedWordsReadable := 0 readyDelay := 0