diff --git a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
index 2a83428..88cad3d 100644
--- a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
+++ b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
@@ -64,6 +64,7 @@ object VexRiscvCachedWishboneForSim{
               catchIllegal      = true,
               catchUnaligned    = true
             ),
+            dBusCmdMasterPipe = true, //required for wishbone
             memoryTranslatorPortConfig = null
             //            memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
             //              portTlbSize = 6