From 5c7e4a0294c785b58b424e49b4696855143370cb Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Tue, 24 Aug 2021 23:24:22 +0200
Subject: [PATCH] #170 wishbone example now set dBusCmdMasterPipe

---
 src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
index 2a83428..88cad3d 100644
--- a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
+++ b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
@@ -64,6 +64,7 @@ object VexRiscvCachedWishboneForSim{
               catchIllegal      = true,
               catchUnaligned    = true
             ),
+            dBusCmdMasterPipe = true, //required for wishbone
             memoryTranslatorPortConfig = null
             //            memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
             //              portTlbSize = 6