From 5cda2632df07888d46af64ea27b8d2a03a5f7ab2 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Sun, 21 May 2017 23:50:40 +0200 Subject: [PATCH] Start implementing debugPlugin test infrastructures --- .../SpinalRiscv/Plugin/DebugPlugin.scala | 132 +++++++++--------- src/main/scala/SpinalRiscv/TopLevel.scala | 2 +- src/test/cpp/regression/main.cpp | 55 +++++++- src/test/cpp/regression/makefile | 5 + 4 files changed, 126 insertions(+), 68 deletions(-) diff --git a/src/main/scala/SpinalRiscv/Plugin/DebugPlugin.scala b/src/main/scala/SpinalRiscv/Plugin/DebugPlugin.scala index a8e11cb..2620028 100644 --- a/src/main/scala/SpinalRiscv/Plugin/DebugPlugin.scala +++ b/src/main/scala/SpinalRiscv/Plugin/DebugPlugin.scala @@ -36,7 +36,7 @@ case class DebugExtensionIo() extends Bundle with IMasterSlave{ } } -class DebugPlugin() extends Plugin[VexRiscv] { +class DebugPlugin(debugClockDomain : ClockDomain) extends Plugin[VexRiscv] { var io : DebugExtensionIo = null @@ -46,7 +46,7 @@ class DebugPlugin() extends Plugin[VexRiscv] { import Riscv._ import pipeline.config._ - io = slave(DebugExtensionIo()) + io = slave(DebugExtensionIo()).setName("debug") val decoderService = pipeline.service(classOf[DecoderService]) @@ -64,83 +64,83 @@ class DebugPlugin() extends Plugin[VexRiscv] { import pipeline._ import pipeline.config._ - val busReadDataReg = Reg(Bits(32 bit)) - when(writeBack.arbitration.isValid){ - busReadDataReg := writeBack.output(REGFILE_WRITE_DATA) - } - io.bus.cmd.ready := True - io.bus.rsp.data := busReadDataReg + debugClockDomain {pipeline plug new Area{ + val busReadDataReg = Reg(Bits(32 bit)) + when(writeBack.arbitration.isValid) { + busReadDataReg := writeBack.output(REGFILE_WRITE_DATA) + } + io.bus.cmd.ready := True + io.bus.rsp.data := busReadDataReg - val insertDecodeInstruction = False - val firstCycle = RegNext(False) setWhen(io.bus.cmd.ready) - val resetIt = RegInit(False) - val haltIt = RegInit(False) - val flushIt = RegNext(False) - val stepIt = RegInit(False) + val insertDecodeInstruction = False + val firstCycle = RegNext(False) setWhen (io.bus.cmd.ready) + val resetIt = RegInit(False) + val haltIt = RegInit(False) + val stepIt = RegInit(False) - val isPipActive = RegNext(List(fetch,decode,execute,memory,writeBack).map(_.arbitration.isValid).orR) - val isPipBusy = isPipActive || RegNext(isPipActive) - val haltedByBreak = RegInit(False) + val isPipActive = RegNext(List(fetch, decode, execute, memory, writeBack).map(_.arbitration.isValid).orR) + val isPipBusy = isPipActive || RegNext(isPipActive) + val haltedByBreak = RegInit(False) - when(io.bus.cmd.valid) { - switch(io.bus.cmd.address(2 downto 2)) { - is(0){ - when(io.bus.cmd.wr){ - flushIt := io.bus.cmd.data(2) - stepIt := io.bus.cmd.data(4) - resetIt setWhen(io.bus.cmd.data(16)) clearWhen(io.bus.cmd.data(24)) - haltIt setWhen(io.bus.cmd.data(17)) clearWhen(io.bus.cmd.data(25)) - haltedByBreak clearWhen(io.bus.cmd.data(25)) - } otherwise{ - busReadDataReg(0) := resetIt - busReadDataReg(1) := haltIt - busReadDataReg(2) := isPipBusy - busReadDataReg(3) := haltedByBreak - busReadDataReg(4) := stepIt + when(io.bus.cmd.valid) { + switch(io.bus.cmd.address(2 downto 2)) { + is(0) { + when(io.bus.cmd.wr) { + stepIt := io.bus.cmd.data(4) + resetIt setWhen (io.bus.cmd.data(16)) clearWhen (io.bus.cmd.data(24)) + haltIt setWhen (io.bus.cmd.data(17)) clearWhen (io.bus.cmd.data(25)) + haltedByBreak clearWhen (io.bus.cmd.data(25)) + } otherwise { + busReadDataReg(0) := resetIt + busReadDataReg(1) := haltIt + busReadDataReg(2) := isPipBusy + busReadDataReg(3) := haltedByBreak + busReadDataReg(4) := stepIt + } } - } - is(1) { - when(io.bus.cmd.wr){ - insertDecodeInstruction := True - val injectedInstructionSent = RegNext(decode.arbitration.isFiring) init(False) - decode.arbitration.haltIt setWhen(!injectedInstructionSent && !RegNext(decode.arbitration.isValid).init(False)) - decode.arbitration.isValid setWhen(firstCycle) - io.bus.cmd.ready := injectedInstructionSent + is(1) { + when(io.bus.cmd.wr) { + insertDecodeInstruction := True + val injectedInstructionSent = RegNext(decode.arbitration.isFiring) init (False) + decode.arbitration.haltIt setWhen (!injectedInstructionSent && !RegNext(decode.arbitration.isValid).init(False)) + decode.arbitration.isValid setWhen (firstCycle) + io.bus.cmd.ready := injectedInstructionSent + } } } } - } - //Assign the bus write data into the register who drive the decode instruction, even if it need to cross some hierarchy (caches) - Component.current.addPrePopTask(() => { - val reg = decode.input(INSTRUCTION).getDrivingReg - reg.component.rework{ - when(insertDecodeInstruction.pull()) { - reg := io.bus.cmd.data.pull() + //Assign the bus write data into the register who drive the decode instruction, even if it need to cross some hierarchy (caches) + Component.current.addPrePopTask(() => { + val reg = decode.input(INSTRUCTION).getDrivingReg + reg.component.rework { + when(insertDecodeInstruction.pull()) { + reg := io.bus.cmd.data.pull() + } } + }) + + + when(execute.arbitration.isFiring && execute.input(IS_EBREAK)) { + prefetch.arbitration.haltIt := True + decode.arbitration.flushAll := True + haltIt := True + haltedByBreak := True } - }) + when(haltIt) { + prefetch.arbitration.haltIt := True + } - when(execute.arbitration.isFiring && execute.input(IS_EBREAK)){ - prefetch.arbitration.haltIt := True - decode.arbitration.flushAll := True - haltIt := True - haltedByBreak := True - } + when(stepIt && prefetch.arbitration.isFiring) { + haltIt := True + } - when(haltIt){ - prefetch.arbitration.haltIt := True - } + io.resetOut := RegNext(resetIt) - when(stepIt && prefetch.arbitration.isFiring){ - haltIt := True - } - - io.resetOut := RegNext(resetIt) - - when(haltIt || stepIt){ - service(classOf[InterruptionInhibitor]).inhibateInterrupts() - } + when(haltIt || stepIt) { + service(classOf[InterruptionInhibitor]).inhibateInterrupts() + } + }} } } diff --git a/src/main/scala/SpinalRiscv/TopLevel.scala b/src/main/scala/SpinalRiscv/TopLevel.scala index 72e6cfd..23a9bb8 100644 --- a/src/main/scala/SpinalRiscv/TopLevel.scala +++ b/src/main/scala/SpinalRiscv/TopLevel.scala @@ -183,7 +183,7 @@ object TopLevel { new MulPlugin, new DivPlugin, new CsrPlugin(csrConfigAll), -// new DebugPlugin(), + new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new BranchPlugin( earlyBranch = false, catchAddressMisaligned = true, diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index e950e72..342434f 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -137,6 +137,7 @@ double sc_time_stamp(){ class SimElement{ public: virtual void onReset(){} + virtual void postReset(){} virtual void preCycle(){} virtual void postCycle(){} }; @@ -292,9 +293,10 @@ public: top->clk = 0; top->reset = 0; - for(SimElement* simElement : simElements) simElement->onReset(); top->eval(); currentTime = 3; + for(SimElement* simElement : simElements) simElement->onReset(); + top->reset = 1; top->eval(); #ifdef CSR @@ -303,6 +305,8 @@ public: #endif dump(0); top->reset = 0; + for(SimElement* simElement : simElements) simElement->postReset(); + top->eval(); currentTime = 2; @@ -578,6 +582,52 @@ public: #endif +#ifdef DEBUG_PLUGIN +#include +#include +#include +#include + +class DebugPlugin : public SimElement{ +public: + + + Workspace *ws; + VVexRiscv* top; + DebugPlugin(Workspace* ws){ + this->ws = ws; + this->top = ws->top; + top->debugReset = 0; + } + + virtual void onReset(){ + top->debug_bus_cmd_valid = 0; + top->debugReset = 1; + } + + + + virtual void postReset(){ + top->debugReset = 0; + } + + virtual void preCycle(){ + + } + + virtual void postCycle(){ + top->reset = top->debug_resetOut; + + /*input debug_bus_cmd_valid, + output debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output reg debug_resetOut,*/ + } +}; +#endif void Workspace::fillSimELements(){ #ifdef IBUS_SIMPLE @@ -592,6 +642,9 @@ void Workspace::fillSimELements(){ #ifdef DBUS_CACHED simElements.push_back(new DBusCached(this)); #endif + #ifdef DEBUG_PLUGIN + simElements.push_back(new DebugPlugin(this)); + #endif } diff --git a/src/test/cpp/regression/makefile b/src/test/cpp/regression/makefile index 71bd964..937074c 100644 --- a/src/test/cpp/regression/makefile +++ b/src/test/cpp/regression/makefile @@ -4,6 +4,7 @@ TRACE=no TRACE_START=0 CSR=yes MMU=yes +DEBUG_PLUGIN=yes DHRYSTONE=yes FREE_RTOS=no REDO=10 @@ -39,6 +40,10 @@ ifeq ($(MMU),yes) ADDCFLAGS += -CFLAGS -DMMU endif +ifeq ($(DEBUG_PLUGIN),yes) + ADDCFLAGS += -CFLAGS -DDEBUG_PLUGIN +endif + ifeq ($(REF),yes) ADDCFLAGS += -CFLAGS -DREF endif