From 5df56bea79c4c84121143885800e14ef97c11a59 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Thu, 3 Oct 2019 00:20:33 +0200 Subject: [PATCH] Allow getDrivingReg to properly see i$ decode.input(INSTRUCTION) register (used to inject instruction from the debug plugin) --- .../scala/vexriscv/ip/InstructionCache.scala | 18 ++++++++++-------- .../vexriscv/plugin/IBusCachedPlugin.scala | 8 ++++---- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/src/main/scala/vexriscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala index edc33d8..8f55093 100644 --- a/src/main/scala/vexriscv/ip/InstructionCache.scala +++ b/src/main/scala/vexriscv/ip/InstructionCache.scala @@ -22,7 +22,8 @@ case class InstructionCacheConfig( cacheSize : Int, asyncTagMemory : Boolean, twoCycleCache : Boolean = true, twoCycleRam : Boolean = false, - preResetFlush : Boolean = false){ + preResetFlush : Boolean = false, + bypassGen : Boolean = false ){ assert(!(twoCycleRam && !twoCycleCache)) @@ -108,8 +109,8 @@ case class InstructionCacheCpuFetch(p : InstructionCacheConfig) extends Bundle w val isRemoved = Bool() val pc = UInt(p.addressWidth bits) val data = Bits(p.cpuDataWidth bits) - val dataBypassValid = Bool() - val dataBypass = Bits(p.cpuDataWidth bits) + val dataBypassValid = p.bypassGen generate Bool() + val dataBypass = p.bypassGen generate Bits(p.cpuDataWidth bits) val mmuBus = MemoryTranslatorBus() val physicalAddress = UInt(p.addressWidth bits) val cacheMiss, error, mmuRefilling, mmuException, isUser = ifGen(!p.twoCycleCache)(Bool) @@ -415,15 +416,16 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{ val id = OHToUInt(hits) val error = read.waysValues.map(_.tag.error).read(id) val data = read.waysValues.map(_.data).read(id) - val word = data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange)) - io.cpu.fetch.data := (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | word) + val word = if(cpuDataWidth == memDataWidth) CombInit(data) else data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange)) + io.cpu.fetch.data := (if(p.bypassGen) (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | word) else word) if(twoCycleCache){ io.cpu.decode.data := RegNextWhen(io.cpu.fetch.data,!io.cpu.decode.isStuck) } } if(twoCycleRam && wayCount == 1){ - io.cpu.fetch.data := (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | read.waysValues.head.data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange))) + val cacheData = if(cpuDataWidth == memDataWidth) CombInit(read.waysValues.head.data) else read.waysValues.head.data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange)) + io.cpu.fetch.data := (if(p.bypassGen) (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | cacheData) else cacheData) } io.cpu.fetch.mmuBus.cmd.isValid := io.cpu.fetch.isValid @@ -458,8 +460,8 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{ val id = OHToUInt(hits) val error = tags(id).error val data = fetchStage.read.waysValues.map(way => stage(way.data)).read(id) - val word = data.subdivideIn(cpuDataWidth bits).read(io.cpu.decode.pc(memWordToCpuWordRange)) - when(stage(io.cpu.fetch.dataBypassValid)){ + val word = if(cpuDataWidth == memDataWidth) data else data.subdivideIn(cpuDataWidth bits).read(io.cpu.decode.pc(memWordToCpuWordRange)) + if(p.bypassGen) when(stage(io.cpu.fetch.dataBypassValid)){ word := stage(io.cpu.fetch.dataBypass) } io.cpu.decode.data := word diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala index 6a582c8..a7b2194 100644 --- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala @@ -61,7 +61,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, var redoBranch : Flow[UInt] = null var decodeExceptionPort : Flow[ExceptionCause] = null val tightlyCoupledPorts = ArrayBuffer[TightlyCoupledPort]() - + def tightlyGen = tightlyCoupledPorts.nonEmpty def newTightlyCoupledPort(p : TightlyCoupledPortParameter) = { val port = TightlyCoupledPort(p, null) @@ -125,7 +125,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, import pipeline.config._ pipeline plug new FetchArea(pipeline) { - val cache = new InstructionCache(IBusCachedPlugin.this.config) + val cache = new InstructionCache(IBusCachedPlugin.this.config.copy(bypassGen = tightlyGen)) iBus = master(new InstructionCacheMemBus(IBusCachedPlugin.this.config)).setName("iBus") iBus <> cache.io.mem iBus.cmd.address.allowOverride := cache.io.mem.cmd.address @@ -165,8 +165,8 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, val tightlyCoupledHits = RegNextWhen(s0.tightlyCoupledHits, stages(1).input.ready) val tightlyCoupledHit = RegNextWhen(s0.tightlyCoupledHit, stages(1).input.ready) - cache.io.cpu.fetch.dataBypassValid := tightlyCoupledHit - cache.io.cpu.fetch.dataBypass := (if(tightlyCoupledPorts.isEmpty) B(0) else MuxOH(tightlyCoupledHits, tightlyCoupledPorts.map(e => CombInit(e.bus.data)))) + if(tightlyGen) cache.io.cpu.fetch.dataBypassValid := tightlyCoupledHit + if(tightlyGen) cache.io.cpu.fetch.dataBypass := MuxOH(tightlyCoupledHits, tightlyCoupledPorts.map(e => CombInit(e.bus.data))) //Connect fetch cache side cache.io.cpu.fetch.isValid := stages(1).input.valid && !tightlyCoupledHit