From 5e7dd02bf72944bd40bd36fa6d55eb9e476474f4 Mon Sep 17 00:00:00 2001
From: Dolu1990 <papuchoud@hotmail.com>
Date: Wed, 6 Jun 2018 18:30:30 +0200
Subject: [PATCH] Fix relaxedPc/DYNAMIC_TARGET interaction

---
 src/main/scala/vexriscv/TestsWorkspace.scala    |  7 ++++---
 src/main/scala/vexriscv/plugin/Fetcher.scala    |  7 +++++--
 .../scala/vexriscv/TestIndividualFeatures.scala | 17 ++++++++++++++---
 3 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala
index 22e3c89..a50a528 100644
--- a/src/main/scala/vexriscv/TestsWorkspace.scala
+++ b/src/main/scala/vexriscv/TestsWorkspace.scala
@@ -33,12 +33,13 @@ object TestsWorkspace {
         plugins = List(
           new IBusSimplePlugin(
             resetVector = 0x80000000l,
-            relaxedPcCalculation = false,
+            relaxedPcCalculation = true,
+            relaxedBusCmdValid = false,
             prediction = DYNAMIC_TARGET,
             historyRamSizeLog2 = 10,
             catchAccessFault = true,
-            compressedGen = true,
-            busLatencyMin = 3
+            compressedGen = false,
+            busLatencyMin = 1
           ),
 //          new IBusCachedPlugin(
 //            resetVector = 0x80000000l,
diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala
index 8edb6f8..a47e3b1 100644
--- a/src/main/scala/vexriscv/plugin/Fetcher.scala
+++ b/src/main/scala/vexriscv/plugin/Fetcher.scala
@@ -126,18 +126,21 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
         }
       }
 
+      preOutput.valid := RegNext(True) init (False) // && !jump.pcLoad.valid
+      preOutput.payload := pcReg
+
       //application of the selected jump request
       if(predictionPcLoad != null) {
         when(predictionPcLoad.valid) {
           pcReg := predictionPcLoad.payload
+          preOutput.valid := False
         }
       }
       when(jump.pcLoad.valid) {
         pcReg := jump.pcLoad.payload
       }
 
-      preOutput.valid := RegNext(True) init (False) // && !jump.pcLoad.valid
-      preOutput.payload := pcReg
+
     } else new PcFetch{
       //PC calculation without Jump
       val pcReg = Reg(UInt(32 bits)) init(if(resetVector != null) resetVector else externalResetVector) addAttribute(Verilator.public)
diff --git a/src/test/scala/vexriscv/TestIndividualFeatures.scala b/src/test/scala/vexriscv/TestIndividualFeatures.scala
index 4cb8ee1..e975ac3 100644
--- a/src/test/scala/vexriscv/TestIndividualFeatures.scala
+++ b/src/test/scala/vexriscv/TestIndividualFeatures.scala
@@ -202,8 +202,8 @@ class IBusDimension extends VexRiscvDimension("IBus") {
       busLatencyMin = latency,
       injectorStage = injectorStage
     )
-  }) :+ new VexRiscvPosition("FullRelaxed"){
-    override def testParam = "IBUS=SIMPLE"
+  }) :+ new VexRiscvPosition("FullRelaxedDeep"){
+    override def testParam = "IBUS=SIMPLE COMPRESSED=yes"
     override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new IBusSimplePlugin(
       resetVector = 0x80000000l,
       relaxedPcCalculation = true,
@@ -212,10 +212,21 @@ class IBusDimension extends VexRiscvDimension("IBus") {
       catchAccessFault = false,
       compressedGen = true,
       busLatencyMin = 3,
+      injectorStage = false
+    )
+  } :+ new VexRiscvPosition("FullRelaxedStd") {
+    override def testParam = "IBUS=SIMPLE"
+    override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new IBusSimplePlugin(
+      resetVector = 0x80000000l,
+      relaxedPcCalculation = true,
+      relaxedBusCmdValid = true,
+      prediction = STATIC,
+      catchAccessFault = false,
+      compressedGen = false,
+      busLatencyMin = 1,
       injectorStage = true
     )
   }
-
 }