From 5f0aec7570513960af9aa6066dfa1cb3af0d400b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 15 Jul 2020 17:03:05 +0200 Subject: [PATCH] BmbInterconnectGenerator refractoring --- src/main/scala/vexriscv/VexRiscvBmbGenerator.scala | 4 ++-- src/main/scala/vexriscv/demo/smp/Misc.scala | 4 ++-- src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala index 5460299..15fc7c8 100644 --- a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala +++ b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala @@ -1,7 +1,7 @@ package vexriscv import spinal.core._ -import spinal.lib.bus.bmb.{Bmb, BmbAccessCapabilities, BmbAccessParameter, BmbImplicitDebugDecoder, BmbInvalidationParameter, BmbParameter, BmbSmpInterconnectGenerator} +import spinal.lib.bus.bmb.{Bmb, BmbAccessCapabilities, BmbAccessParameter, BmbImplicitDebugDecoder, BmbInvalidationParameter, BmbParameter, BmbInterconnectGenerator} import spinal.lib.bus.misc.AddressMapping import spinal.lib.com.jtag.{Jtag, JtagTapInstructionCtrl} import spinal.lib.generator._ @@ -17,7 +17,7 @@ object VexRiscvBmbGenerator{ val DEBUG_BMB = 4 } -case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbSmpInterconnectGenerator = null) extends Generator { +case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGenerator = null) extends Generator { import VexRiscvBmbGenerator._ val config = Handle[VexRiscvConfig] diff --git a/src/main/scala/vexriscv/demo/smp/Misc.scala b/src/main/scala/vexriscv/demo/smp/Misc.scala index 01135b6..1306fc1 100644 --- a/src/main/scala/vexriscv/demo/smp/Misc.scala +++ b/src/main/scala/vexriscv/demo/smp/Misc.scala @@ -247,7 +247,7 @@ object BmbToLiteDramTester extends App{ } } -case class BmbToLiteDramGenerator(mapping : AddressMapping)(implicit interconnect : BmbSmpInterconnectGenerator) extends Generator{ +case class BmbToLiteDramGenerator(mapping : AddressMapping)(implicit interconnect : BmbInterconnectGenerator) extends Generator{ val liteDramParameter = createDependency[LiteDramNativeParameter] val bmb = produce(logic.io.input) val dram = produceIo(logic.io.output) @@ -269,7 +269,7 @@ case class BmbToLiteDramGenerator(mapping : AddressMapping)(implicit interconnec ) } -case class BmbToWishboneGenerator(mapping : AddressMapping)(implicit interconnect : BmbSmpInterconnectGenerator) extends Generator{ +case class BmbToWishboneGenerator(mapping : AddressMapping)(implicit interconnect : BmbInterconnectGenerator) extends Generator{ val bmb = produce(logic.io.input) val wishbone = produce(logic.io.output) diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala index 78b1ddd..602bd1f 100644 --- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala +++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala @@ -37,7 +37,7 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Generator{ this.onClockDomain(systemCd.outputClockDomain) - implicit val interconnect = BmbSmpInterconnectGenerator() + implicit val interconnect = BmbInterconnectGenerator() val debugBridge = JtagInstructionDebuggerGenerator() onClockDomain(debugCd.outputClockDomain) debugBridge.jtagClockDomain.load(ClockDomain.external("jtag", withReset = false))