From 1017b316b8a7e404a6ac3d8c46f3e5afeed9d9ea Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 15 Jun 2021 15:59:09 +0200 Subject: [PATCH 01/11] version++ --- build.sbt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index 51bd3fe..e4cf8d6 100644 --- a/build.sbt +++ b/build.sbt @@ -1,4 +1,4 @@ -val spinalVersion = "1.4.4" +val spinalVersion = "1.5.1" lazy val root = (project in file(".")). settings( From cdd8a7e94a55992ade6635c18de6144fe82e2170 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 23 Jun 2021 09:04:35 +0200 Subject: [PATCH 02/11] add github action --- .github/workflows/scala.yml | 59 +++++++++++++++++++++++++++++++++++ tools.sh | 62 +++++++++++++++++++++++++++++++++++++ 2 files changed, 121 insertions(+) create mode 100644 .github/workflows/scala.yml create mode 100644 tools.sh diff --git a/.github/workflows/scala.yml b/.github/workflows/scala.yml new file mode 100644 index 0000000..06d1ae4 --- /dev/null +++ b/.github/workflows/scala.yml @@ -0,0 +1,59 @@ +name: Scala CI + +on: [push, pull_request] + +jobs: + build: + runs-on: ubuntu-latest + timeout-minutes: 90 + + steps: + - uses: actions/checkout@v2 + with: + submodules: 'recursive' + + - name: Set up JDK 11 + uses: actions/setup-java@v2 + with: + java-version: '11' + distribution: 'adopt' + + - name: Cache pip + uses: actions/cache@v2 + with: + path: ~/.cache/pip + key: ${{ runner.os }}-pip-v2 + restore-keys: | + ${{ runner.os }}-pip- + + - name: Cache SBT + uses: actions/cache@v2 + with: + path: | + ~/.ivy2/cache + ~/.sbt + key: ${{ runner.os }}-sbt-${{ hashFiles('**/build.sbt') }} + + - name: Cache tools + id: tools + uses: actions/cache@v2 + with: + path: | + ~/tools + key: ${{ runner.os }}-tools_v2 + + - name: Setup env + run: echo "$HOME/tools/bin" >> $GITHUB_PATH + + - name: Install cached tools + if: steps.tools.outputs.cache-hit != 'true' + run: source tools.sh && (cd ~/ && install_verilator) + + - name: Install uncached tools + run: (cd .. && git clone https://github.com/SpinalHDL/SpinalHDL.git -b dev) + + - name: Compile tests + run: sbt "+test:compile" + + - name: Run tests + run: sbt "+test" diff --git a/tools.sh b/tools.sh new file mode 100644 index 0000000..ebe0592 --- /dev/null +++ b/tools.sh @@ -0,0 +1,62 @@ +#!/bin/sh + +install_verilator(){ + sudo apt install -y git make autoconf g++ flex libfl-dev bison # First time prerequisites + git clone http://git.veripool.org/git/verilator # Only first time + unset VERILATOR_ROOT # For bash + cd verilator + git pull # Make sure we're up-to-date + git checkout v4.040 + autoconf # Create ./configure script + ./configure --prefix ~/tools + make -j$(nproc) + make install + cd .. +} + +install_ghdl(){ + sudo apt install -y gnat-9 libgnat-9 zlib1g-dev libboost-dev + git clone https://github.com/ghdl/ghdl ghdl-build && cd ghdl-build + git reset --hard "0316f95368837dc163173e7ca52f37ecd8d3591d" + mkdir build + cd build + ../configure --prefix=~/tools + make -j$(nproc) + make install + cd .. +} + +install_iverilog(){ + sudo apt install -y gperf readline-common bison flex libfl-dev + curl -fsSL https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz | tar -xvz + cd iverilog-10_3 + autoconf + ./configure --prefix ~/tools + make -j$(nproc) + make install + cd .. +} + +install_cocotb(){ + pip3 install --user cocotb + sudo apt install -y git make gcc g++ swig python3-dev +} + +purge_cocotb(){ + # Force cocotb to compile VPI to avoid race condition when tests are start in parallel + cd tester/src/test/python/spinal/Dummy + make TOPLEVEL_LANG=verilog + make TOPLEVEL_LANG=vhdl + cd ../../../../../.. +} + +install_packages(){ + sudo apt install -y gnat-9 libgnat-9 zlib1g-dev libboost-dev +} + +install_tools(){ + install_verilator + install_ghdl + install_iverilog + install_cocotb +} \ No newline at end of file From df7ac05db988b3c3bbbf80b782d5b1f2a2c1a0c9 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 23 Jun 2021 11:48:38 +0200 Subject: [PATCH 03/11] Update 2.13 compatibility --- build.sbt | 4 ++-- src/main/scala/vexriscv/demo/Briey.scala | 8 ++++---- src/main/scala/vexriscv/demo/Murax.scala | 4 ++-- src/main/scala/vexriscv/demo/MuraxUtiles.scala | 2 +- src/test/scala/vexriscv/DhrystoneBench.scala | 4 ++-- .../scala/vexriscv/TestIndividualFeatures.scala | 14 ++++++++------ src/test/scala/vexriscv/ip/fpu/FpuTest.scala | 5 +++-- 7 files changed, 22 insertions(+), 19 deletions(-) diff --git a/build.sbt b/build.sbt index e4cf8d6..0b0f302 100644 --- a/build.sbt +++ b/build.sbt @@ -10,8 +10,8 @@ lazy val root = (project in file(".")). scalacOptions += s"-Xplugin:${new File(baseDirectory.value + s"/../SpinalHDL/idslplugin/target/scala-2.11/spinalhdl-idsl-plugin_2.11-$spinalVersion.jar")}", scalacOptions += s"-Xplugin-require:idsl-plugin", libraryDependencies ++= Seq( - "org.scalatest" % "scalatest_2.11" % "2.2.1", - "org.yaml" % "snakeyaml" % "1.8" + "org.scalatest" %% "scalatest" % "3.2.5", + "org.yaml" % "snakeyaml" % "1.8" ), name := "VexRiscv" ).dependsOn(spinalHdlIdslPlugin, spinalHdlSim,spinalHdlCore,spinalHdlLib) diff --git a/src/main/scala/vexriscv/demo/Briey.scala b/src/main/scala/vexriscv/demo/Briey.scala index dd794a6..76c688d 100644 --- a/src/main/scala/vexriscv/demo/Briey.scala +++ b/src/main/scala/vexriscv/demo/Briey.scala @@ -174,9 +174,9 @@ class Briey(config: BrieyConfig) extends Component{ val io = new Bundle{ //Clocks / reset - val asyncReset = in Bool - val axiClk = in Bool - val vgaClk = in Bool + val asyncReset = in Bool() + val axiClk = in Bool() + val vgaClk = in Bool() //Main components IO val jtag = slave(Jtag()) @@ -188,7 +188,7 @@ class Briey(config: BrieyConfig) extends Component{ val uart = master(Uart()) val vga = master(Vga(vgaRgbConfig)) val timerExternal = in(PinsecTimerCtrlExternal()) - val coreInterrupt = in Bool + val coreInterrupt = in Bool() } val resetCtrlClockDomain = ClockDomain( diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 82bceb3..05c8e00 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -157,8 +157,8 @@ case class Murax(config : MuraxConfig) extends Component{ val io = new Bundle { //Clocks / reset - val asyncReset = in Bool - val mainClk = in Bool + val asyncReset = in Bool() + val mainClk = in Bool() //Main components IO val jtag = slave(Jtag()) diff --git a/src/main/scala/vexriscv/demo/MuraxUtiles.scala b/src/main/scala/vexriscv/demo/MuraxUtiles.scala index 1e22157..22bc438 100644 --- a/src/main/scala/vexriscv/demo/MuraxUtiles.scala +++ b/src/main/scala/vexriscv/demo/MuraxUtiles.scala @@ -142,7 +142,7 @@ class MuraxApb3Timer extends Component{ addressWidth = 8, dataWidth = 32 )) - val interrupt = out Bool + val interrupt = out Bool() } val prescaler = Prescaler(16) diff --git a/src/test/scala/vexriscv/DhrystoneBench.scala b/src/test/scala/vexriscv/DhrystoneBench.scala index a98377c..48d1b67 100644 --- a/src/test/scala/vexriscv/DhrystoneBench.scala +++ b/src/test/scala/vexriscv/DhrystoneBench.scala @@ -2,13 +2,13 @@ package vexriscv import java.io.File -import org.scalatest.FunSuite +import org.scalatest.funsuite.AnyFunSuite import spinal.core.SpinalVerilog import vexriscv.demo._ import scala.sys.process._ -class DhrystoneBench extends FunSuite { +class DhrystoneBench extends AnyFunSuite { def doCmd(cmd: String): String = { val stdOut = new StringBuilder() class Logger extends ProcessLogger { diff --git a/src/test/scala/vexriscv/TestIndividualFeatures.scala b/src/test/scala/vexriscv/TestIndividualFeatures.scala index 71c6697..bd5acb0 100644 --- a/src/test/scala/vexriscv/TestIndividualFeatures.scala +++ b/src/test/scala/vexriscv/TestIndividualFeatures.scala @@ -3,7 +3,9 @@ package vexriscv import java.io.{File, OutputStream} import java.util.concurrent.{ForkJoinPool, TimeUnit} import org.apache.commons.io.FileUtils -import org.scalatest.{BeforeAndAfterAll, FunSuite, ParallelTestExecution, Tag, Transformer} +import org.scalatest.{BeforeAndAfterAll, ParallelTestExecution, Tag, Transformer} +import org.scalatest.funsuite.AnyFunSuite + import spinal.core._ import spinal.lib.DoCmd import vexriscv.demo._ @@ -617,7 +619,7 @@ object PlayFuture extends App{ Thread.sleep(8000) } -class MultithreadedFunSuite(threadCount : Int) extends FunSuite { +class MultithreadedFunSuite(threadCount : Int) extends AnyFunSuite { val finalThreadCount = if(threadCount > 0) threadCount else { new oshi.SystemInfo().getHardware.getProcessor.getLogicalProcessorCount } @@ -650,7 +652,7 @@ class MultithreadedFunSuite(threadCount : Int) extends FunSuite { } } - override protected def test(testName: String, testTags: Tag*)(testFun: => Unit) { + def testMp(testName: String, testTags: Tag*)(testFun: => Unit) { val job = new Job(testFun) super.test(testName, testTags :_*)(job.join()) } @@ -662,7 +664,7 @@ class MultithreadedFunSuite(threadCount : Int) extends FunSuite { class FunTestPara extends MultithreadedFunSuite(3){ def createTest(name : String): Unit ={ - test(name){ + testMp(name){ for(i <- 0 to 4) { println(s"$name $i") Thread.sleep(500) @@ -745,7 +747,7 @@ class TestIndividualFeatures extends MultithreadedFunSuite(sys.env.getOrElse("VE stdOut.toString() } - test(prefix + name) { + testMp(prefix + name) { println("START TEST " + prefix + name) //Cleanup @@ -787,7 +789,7 @@ class TestIndividualFeatures extends MultithreadedFunSuite(sys.env.getOrElse("VE val rand = new Random(seed) - test("Info"){ + testMp("Info"){ println(s"MAIN_SEED=$seed") } println(s"Seed=$seed") diff --git a/src/test/scala/vexriscv/ip/fpu/FpuTest.scala b/src/test/scala/vexriscv/ip/fpu/FpuTest.scala index 280a5fe..11182ac 100644 --- a/src/test/scala/vexriscv/ip/fpu/FpuTest.scala +++ b/src/test/scala/vexriscv/ip/fpu/FpuTest.scala @@ -5,7 +5,7 @@ import java.lang import java.util.Scanner import org.apache.commons.io.FileUtils -import org.scalatest.FunSuite +import org.scalatest.funsuite.AnyFunSuite import spinal.core.SpinalEnumElement import spinal.core.sim._ import spinal.core._ @@ -18,9 +18,10 @@ import scala.collection.mutable import scala.collection.mutable.ArrayBuffer import scala.sys.process.ProcessLogger import scala.util.Random +import org.scalatest.funsuite.AnyFunSuite //TODO Warning DataCache write aggregation will disable itself -class FpuTest extends FunSuite{ +class FpuTest extends AnyFunSuite{ val b2f = lang.Float.intBitsToFloat(_) val b2d = lang.Double.longBitsToDouble(_) From 3702ea03c0a4cae0e9a18e129932edbb32bea765 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 23 Jun 2021 11:48:53 +0200 Subject: [PATCH 04/11] Fix github actions --- .github/workflows/scala.yml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/.github/workflows/scala.yml b/.github/workflows/scala.yml index 06d1ae4..3c203f5 100644 --- a/.github/workflows/scala.yml +++ b/.github/workflows/scala.yml @@ -55,5 +55,15 @@ jobs: - name: Compile tests run: sbt "+test:compile" - - name: Run tests - run: sbt "+test" + - name: Test Dhrystones + run: make regression_dhrystone -C scripts/regression + + - name: Test Baremetal + run: make regression_random_baremetal -C scripts/regression + + - name: Test Machine OS + run: make regression_random_machine_os -C scripts/regression + + - name: Test Linux + run: make regression_random_linux -C scripts/regression + From 551e76d244912f694f01c2be5d569c1e6c4e3cd9 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 2 Jul 2021 19:04:30 +0200 Subject: [PATCH 05/11] VexRiscvSmpCluster add a few options --- .../demo/smp/VexRiscvSmpCluster.scala | 27 ++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala index b724c45..55b2c8d 100644 --- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala +++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala @@ -188,6 +188,31 @@ object VexRiscvSmpClusterGen { assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes") assert(!(withDouble && !withFloat)) + val csrConfig = if(withSupervisor){ + CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}s")).copy(utimeAccess = CsrAccess.READ_ONLY) + } else { + CsrPluginConfig( + catchIllegalAccess = true, + mvendorid = null, + marchid = null, + mimpid = null, + mhartid = 0, + misaExtensionsInit = 0, + misaAccess = CsrAccess.NONE, + mtvecAccess = CsrAccess.READ_WRITE, + mtvecInit = null, + mepcAccess = CsrAccess.READ_WRITE, + mscratchGen = false, + mcauseAccess = CsrAccess.READ_ONLY, + mbadaddrAccess = CsrAccess.READ_ONLY, + mcycleAccess = CsrAccess.NONE, + minstretAccess = CsrAccess.NONE, + ecallGen = true, + wfiGenAsWait = false, + wfiGenAsNop = true, + ucycleAccess = CsrAccess.NONE + ) + } val config = VexRiscvConfig( plugins = List( if(withMmu)new MmuPlugin( @@ -283,7 +308,7 @@ object VexRiscvSmpClusterGen { mulUnrollFactor = 32, divUnrollFactor = 1 ), - new CsrPlugin(CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}s")).copy(utimeAccess = CsrAccess.READ_ONLY)), + new CsrPlugin(csrConfig), new BranchPlugin( earlyBranch = earlyBranch, catchAddressMisaligned = true, From c79357d1b2ae687c01152bd5034c7ef51ac3f430 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 5 Jul 2021 12:38:54 +0200 Subject: [PATCH 06/11] VexRiscvSmpClusterGen no support atomic less configs --- src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala index d17e4fb..cb89da9 100644 --- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala +++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala @@ -167,6 +167,7 @@ object VexRiscvSmpClusterGen { dBusWidth : Int = 64, loadStoreWidth : Int = 32, coherency : Boolean = true, + atomic : Boolean = true, iCacheSize : Int = 8192, dCacheSize : Int = 8192, iCacheWays : Int = 2, @@ -270,9 +271,9 @@ object VexRiscvSmpClusterGen { catchAccessError = true, catchIllegal = true, catchUnaligned = true, - withLrSc = true, - withAmo = true, - withExclusive = coherency, + withLrSc = atomic, + withAmo = atomic, + withExclusive = atomic, withInvalidate = coherency, withWriteAggregation = dBusWidth > 32 ), From 28a75afe7aaab08aac34fb20a3e0f11947cd24d4 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 5 Jul 2021 14:17:48 +0200 Subject: [PATCH 07/11] reduce regression time --- .github/workflows/scala.yml | 2 +- scripts/regression/regression.mk | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/scala.yml b/.github/workflows/scala.yml index 3c203f5..2d4547f 100644 --- a/.github/workflows/scala.yml +++ b/.github/workflows/scala.yml @@ -5,7 +5,7 @@ on: [push, pull_request] jobs: build: runs-on: ubuntu-latest - timeout-minutes: 90 + timeout-minutes: 120 steps: - uses: actions/checkout@v2 diff --git a/scripts/regression/regression.mk b/scripts/regression/regression.mk index 8e3fba8..89e760d 100644 --- a/scripts/regression/regression.mk +++ b/scripts/regression/regression.mk @@ -11,7 +11,7 @@ regression_random: regression_random_linux: cd ../.. - export VEXRISCV_REGRESSION_CONFIG_COUNT=3 + export VEXRISCV_REGRESSION_CONFIG_COUNT=2 export VEXRISCV_REGRESSION_CONFIG_LINUX_RATE=1.0 export VEXRISCV_REGRESSION_CONFIG_SECURE_RATE=0.0 export VEXRISCV_REGRESSION_FREERTOS_COUNT=1 @@ -22,7 +22,7 @@ regression_random_linux: regression_random_machine_os: cd ../.. - export VEXRISCV_REGRESSION_CONFIG_COUNT=15 + export VEXRISCV_REGRESSION_CONFIG_COUNT=10 export VEXRISCV_REGRESSION_CONFIG_LINUX_RATE=0.0 export VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE=1.0 export VEXRISCV_REGRESSION_CONFIG_SECURE_RATE=0.0 @@ -33,7 +33,7 @@ regression_random_machine_os: regression_random_baremetal: cd ../.. - export VEXRISCV_REGRESSION_CONFIG_COUNT=40 + export VEXRISCV_REGRESSION_CONFIG_COUNT=30 export VEXRISCV_REGRESSION_CONFIG_LINUX_RATE=0.0 export VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE=0.0 export VEXRISCV_REGRESSION_CONFIG_SECURE_RATE=0.0 From 9bc7dce857e7f6032a039d48d8eb0f8b28ea4e59 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 8 Jul 2021 09:47:54 +0200 Subject: [PATCH 08/11] Update README.md --- README.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 4fdeec2..1add93b 100644 --- a/README.md +++ b/README.md @@ -169,8 +169,9 @@ sudo update-alternatives --config java sudo update-alternatives --config javac # Install SBT - https://www.scala-sbt.org/ -echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list -sudo apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823 +echo "deb https://repo.scala-sbt.org/scalasbt/debian all main" | sudo tee /etc/apt/sources.list.d/sbt.list +echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | sudo tee /etc/apt/sources.list.d/sbt_old.list +curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo apt-key add sudo apt-get update sudo apt-get install sbt @@ -1196,4 +1197,4 @@ For more documentation, check src/main/scala/vexriscv/plugin/AesPlugin.scala, a It was also ported on libressl via the following patch : -Speed up of 4 was observed in libressl running in linux. \ No newline at end of file +Speed up of 4 was observed in libressl running in linux. From 91b3e79485d7d35758c16c97e300dab265d81e56 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 11 Jul 2021 21:55:13 +0200 Subject: [PATCH 09/11] SpinalHDL version++ --- build.sbt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index 0b0f302..293a83f 100644 --- a/build.sbt +++ b/build.sbt @@ -1,4 +1,4 @@ -val spinalVersion = "1.5.1" +val spinalVersion = "1.6.1" lazy val root = (project in file(".")). settings( From 0cdad37fffdc42e5fe1b23db674f25d223d8526c Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 11 Jul 2021 21:55:33 +0200 Subject: [PATCH 10/11] VexRiscvSmpClusterGen now implement ebreak --- src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala index cb89da9..5aacc2b 100644 --- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala +++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala @@ -214,6 +214,7 @@ object VexRiscvSmpClusterGen { mcycleAccess = CsrAccess.NONE, minstretAccess = CsrAccess.NONE, ecallGen = true, + ebreakGen = true, wfiGenAsWait = false, wfiGenAsNop = true, ucycleAccess = CsrAccess.NONE From 66bcd7fca7f7902f5a4fd586f3578543cd04d1ca Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 20 Jul 2021 10:14:54 +0200 Subject: [PATCH 11/11] readme: add the tom link about JTAG and GDB --- README.md | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/README.md b/README.md index 1add93b..8cb14bd 100644 --- a/README.md +++ b/README.md @@ -300,6 +300,7 @@ To create a new debug configuration: You can use the Eclipse + Zylin embedded CDT plugin to do it (http://opensource.zylin.com/embeddedcdt.html). Tested with Helios Service Release 2 (http://www.Eclipse.org/downloads/download.php?file=/technology/epp/downloads/release/helios/SR2/Eclipse-cpp-helios-SR2-linux-gtk-x86_64.tar.gz) and the corresponding zylin plugin. To following commands will download Eclipse and install the plugin. + ```sh wget http://www.eclipse.org/downloads/download.php?file=/technology/epp/downloads/release/helios/SR2/eclipse-cpp-helios-SR2-linux-gtk-x86_64.tar.gz tar -xvzf download.php?file=%2Ftechnology%2Fepp%2Fdownloads%2Frelease%2Fhelios%2FSR2%2Feclipse-cpp-helios-SR2-linux-gtk-x86_64.tar.gz @@ -311,6 +312,10 @@ See https://drive.google.com/drive/folders/1NseNHH05B6lmIXqQFVwK8xRjWE4ydeG-?usp Note that sometimes Eclipse needs to be restarted in order to be able to place new breakpoints. +If you want to get more information about how all this JTAG / GDB stuff work, you can find great blog about it here : + + + ## Briey SoC As a demonstration, a SoC named Briey is implemented in `src/main/scala/vexriscv/demo/Briey.scala`. This SoC is very similar to the [Pinsec SoC](https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Legacy/pinsec/hardware_toplevel.html#):