diff --git a/src/main/scala/vexriscv/demo/Briey.scala b/src/main/scala/vexriscv/demo/Briey.scala
index 40da56a..709cb23 100644
--- a/src/main/scala/vexriscv/demo/Briey.scala
+++ b/src/main/scala/vexriscv/demo/Briey.scala
@@ -51,56 +51,52 @@ object BrieyConfig{
       ),
       cpuPlugins = ArrayBuffer(
         new PcManagerSimplePlugin(0x80000000l, false),
-        new IBusSimplePlugin(
+        //          new IBusSimplePlugin(
+        //            interfaceKeepData = false,
+        //            catchAccessFault = true
+        //          ),
+        new IBusCachedPlugin(
           resetVector = 0x80000000l,
-          cmdForkOnSecondStage = false,
-          cmdForkPersistence = true,
-          catchAccessFault = true,
-          compressedGen = true
-        ),
-//        new IBusCachedPlugin(
-//          resetVector = 0x80000000l,
-//          prediction = STATIC,
-//          compressedGen = true,
-//          config = InstructionCacheConfig(
-//            cacheSize = 4096,
-//            bytePerLine =32,
-//            wayCount = 1,
-//            addressWidth = 32,
-//            cpuDataWidth = 32,
-//            memDataWidth = 32,
-//            catchIllegalAccess = true,
-//            catchAccessFault = true,
-//            asyncTagMemory = false,
-//            twoCycleRam = true,
-//            twoCycleCache = true
-//          )
+          prediction = STATIC,
+          config = InstructionCacheConfig(
+            cacheSize = 4096,
+            bytePerLine =32,
+            wayCount = 1,
+            addressWidth = 32,
+            cpuDataWidth = 32,
+            memDataWidth = 32,
+            catchIllegalAccess = true,
+            catchAccessFault = true,
+            asyncTagMemory = false,
+            twoCycleRam = true,
+            twoCycleCache = true
+          )
           //            askMemoryTranslation = true,
           //            memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
           //              portTlbSize = 4
           //            )
-//        ),
-                            new DBusSimplePlugin(
-                              catchAddressMisaligned = true,
-                              catchAccessFault = true
-                            ),
-//        new DBusCachedPlugin(
-//          config = new DataCacheConfig(
-//            cacheSize         = 4096,
-//            bytePerLine       = 32,
-//            wayCount          = 1,
-//            addressWidth      = 32,
-//            cpuDataWidth      = 32,
-//            memDataWidth      = 32,
-//            catchAccessError  = true,
-//            catchIllegal      = true,
-//            catchUnaligned    = true
-//          ),
-//          memoryTranslatorPortConfig = null
-//          //            memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
-//          //              portTlbSize = 6
-//          //            )
-//        ),
+        ),
+        //                    new DBusSimplePlugin(
+        //                      catchAddressMisaligned = true,
+        //                      catchAccessFault = true
+        //                    ),
+        new DBusCachedPlugin(
+          config = new DataCacheConfig(
+            cacheSize         = 4096,
+            bytePerLine       = 32,
+            wayCount          = 1,
+            addressWidth      = 32,
+            cpuDataWidth      = 32,
+            memDataWidth      = 32,
+            catchAccessError  = true,
+            catchIllegal      = true,
+            catchUnaligned    = true
+          ),
+          memoryTranslatorPortConfig = null
+          //            memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
+          //              portTlbSize = 6
+          //            )
+        ),
         new StaticMemoryTranslatorPlugin(
           ioRange      = _(31 downto 28) === 0xF
         ),
@@ -108,7 +104,7 @@ object BrieyConfig{
           catchIllegalInstruction = true
         ),
         new RegFilePlugin(
-          regFileReadyKind = plugin.ASYNC,
+          regFileReadyKind = plugin.SYNC,
           zeroBoot = false
         ),
         new IntAluPlugin,
@@ -204,7 +200,7 @@ class Briey(config: BrieyConfig) extends Component{
 
   val resetCtrl = new ClockingArea(resetCtrlClockDomain) {
     val systemResetUnbuffered  = False
-//    val coreResetUnbuffered = False
+    //    val coreResetUnbuffered = False
 
     //Implement an counter to keep the reset axiResetOrder high 64 cycles
     // Also this counter will automaticly do a reset when the system boot.