From 5f67075e3094f1f31b7fe9f480e08fc5c32b28c3 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 1 Mar 2023 13:56:25 +0100 Subject: [PATCH] Fix FPU with F64 support, not removing mantissa precision from F32 #317 --- src/main/scala/vexriscv/ip/fpu/FpuCore.scala | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/ip/fpu/FpuCore.scala b/src/main/scala/vexriscv/ip/fpu/FpuCore.scala index a9e9959..9cdaab5 100644 --- a/src/main/scala/vexriscv/ip/fpu/FpuCore.scala +++ b/src/main/scala/vexriscv/ip/fpu/FpuCore.scala @@ -1688,7 +1688,12 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{ port.valid := input.valid && input.write port.address := input.source @@ input.rd port.data.value := input.value - if(p.withDouble) port.data.boxed := input.format === FpuFormat.FLOAT + if(p.withDouble) { + port.data.boxed := input.format === FpuFormat.FLOAT + when(port.data.boxed){ + port.data.value.mantissa(p.internalMantissaSize-23-1 downto 0) := 0 + } + } val randomSim = p.sim generate (in UInt(p.internalMantissaSize bits)) if(p.sim) when(port.data.value.isZero || port.data.value.isInfinity){