diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala
index c7d3448..710112b 100644
--- a/src/main/scala/vexriscv/demo/SynthesisBench.scala
+++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala
@@ -154,7 +154,7 @@ object MuraxSynthesisBench {
       override def getName(): String = "Murax"
       override def getRtlPath(): String = "Murax.v"
       SpinalVerilog({
-        val murax = new Murax(MuraxConfig.defsbault).setDefinitionName(getRtlPath().split("\\.").head)
+        val murax = new Murax(MuraxConfig.default).setDefinitionName(getRtlPath().split("\\.").head)
         murax.io.mainClk.setName("clk")
         murax
       })