From 60a41bfc75a3dd1e6f2945545d9348bc4c809007 Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Fri, 5 Apr 2019 18:11:10 +0200
Subject: [PATCH] rework i$ flush

---
 .../scala/vexriscv/ip/InstructionCache.scala  | 22 +++++++++----------
 .../vexriscv/plugin/IBusCachedPlugin.scala    | 15 ++-----------
 2 files changed, 13 insertions(+), 24 deletions(-)

diff --git a/src/main/scala/vexriscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala
index 08683c4..b5b4e23 100644
--- a/src/main/scala/vexriscv/ip/InstructionCache.scala
+++ b/src/main/scala/vexriscv/ip/InstructionCache.scala
@@ -249,7 +249,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
   import p._
   assert(cpuDataWidth == memDataWidth, "Need testing")
   val io = new Bundle{
-    val flush = slave(InstructionCacheFlushBus())
+    val flush = in Bool()
     val cpu = slave(InstructionCacheCpuBus(p))
     val mem = master(InstructionCacheMemBus(p))
   }
@@ -300,15 +300,16 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
     val valid = RegInit(False) clearWhen(fire)
     val address = Reg(UInt(addressWidth bits))
     val hadError = RegInit(False) clearWhen(fire)
+    val flushPending = RegInit(True)
 
     when(io.cpu.fill.valid){
       valid := True
       address := io.cpu.fill.payload
     }
 
-    io.cpu.prefetch.haltIt setWhen(valid)
+    io.cpu.prefetch.haltIt setWhen(valid || flushPending)
 
-    val flushCounter = Reg(UInt(log2Up(wayLineCount) + 1 bit)) init(if(preResetFlush) wayLineCount else 0)
+    val flushCounter = Reg(UInt(log2Up(wayLineCount) + 1 bit))
     when(!flushCounter.msb){
       io.cpu.prefetch.haltIt := True
       flushCounter := flushCounter + 1
@@ -316,17 +317,16 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
     when(!RegNext(flushCounter.msb)){
       io.cpu.prefetch.haltIt := True
     }
-    val flushFromInterface = RegInit(False)
-    io.flush.cmd.ready := !(valid || io.cpu.fetch.isValid) //io.cpu.fetch.isValid will avoid bug on first cycle miss
-    when(io.flush.cmd.valid){
+
+    when(io.flush){
       io.cpu.prefetch.haltIt := True
-      when(io.flush.cmd.ready){
-        flushCounter := 0
-        flushFromInterface := True
-      }
+      flushPending := True
     }
 
-    io.flush.rsp := flushCounter.msb.rise && flushFromInterface
+    when(flushPending && !(valid || io.cpu.fetch.isValid) ){
+      flushCounter := 0
+      flushPending := False
+    }
 
 
 
diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
index 07babf9..e725609 100644
--- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
@@ -242,19 +242,8 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
         cache.io.cpu.fetch.mmuBus.rsp.refilling := False
       }
 
-      val flushStage = if(memory != null) memory else execute
-      flushStage plug new Area {
-        import flushStage._
-
-        cache.io.flush.cmd.valid := False
-        when(arbitration.isValid && input(FLUSH_ALL)) {
-          cache.io.flush.cmd.valid := True
-
-          when(!cache.io.flush.cmd.ready) {
-            arbitration.haltItself := True
-          }
-        }
-      }
+      val flushStage = decode
+      cache.io.flush := flushStage.arbitration.isValid && flushStage.input(FLUSH_ALL)
     }
   }
 }